Now that CES is done for another year, it is worth remembering that the diversity of solutions on display and the proliferation of new device experiences at ever lower costs is due to semiconductor vendors being able to leverage the enormous investments that the manufacturing vendors make to continuously improve transistor density and performance at ever smaller process nodes.
TSMC's ability to continue the scaling at the same pace as Intel had been called into doubt late last year by Intel, who also estimated it had a 3.5-year lead in manufacturing. Last week Dr Mark Liu of TSMC decided to put the record straight during an investor event. Mr. Liu explain that today TSMC is manufacturing with 20SoC process, claimed as the highest density process today, and that the next step to 16FinFET would provide further reductions in chip area. (Q4 2013 earnings report http://www.tsmc.com/english/investorRelations/index.htm)
According to Dr Liu TSMC's 16FinFET process is now product qualified and leverages their grand alliance program of EDA vendors, customers and IP providers. TSMC will be quickly ramping multiple tape outs across industry segments, and already have more than 20 customer tape outs scheduled for 2014. TSMC’s transistor improvements from 20SoC to 16FinFET can reduce the area by 15% giving continued area scaling as opposed to the FUD from Intel that TSMC's scaling stalls at the transition point. SemiWiki - TSMC Responds to Intel's 14nm Density Claim
What I find most interesting is the broad range of applications TSMC’s horizontal business model supports. It seems that TSMC's customers are about to utilize 16FinFET not just in mobile baseband solutions, mobile application processor, but also graphics, networking FPGAs and servers being listed amongst the markets being addressed
It does not stop there, Dr Liu went on to further announce that 10nmFinFET will be ready before the end of 2015, ensuring that TSMC is operating at the leading edge of manufacturing processes and the benefit will be readily felt across the multitude of markets where TSMC's customers operate. This news fits with the need to provide choice across multiple markets at a variety of nodes to address the needs and desires of 7 billion people. Innovation isn’t going to stop, and ARM’s foundry partners are showing they can continue to provide the breadth of technology solutions to address diverse markets.
Confirmed for the third quarter of this year Good, really good news !
I believe the 10nm at the end of 2015 date means when they start their year long test and fix to prepare for volume production. It is the date at which one can start doing proper design of a SoC for the actual process but the end of 2016/beginning of 2017 would be when volume starts ramping up. That's supposing things go to plan - EUV doesn't seem to be ready for the big time even for Intel, triple patterning sounds difficult and expensive, and anyway the tiny sizes will accentuate random variation problems. I must admit I'm more excited by 3D die stacking for the moment.
I saw a nice way of measuring a nanometer - your fingernails grow a nanometer a second. So you'd have to wait 10 whole seconds for feature sizes at 10nm ;-)
... Just came back and had a look at what I wrote and it sounds rather negative. and really I'm not - I think the news is great. I'm absolutely amazed at how they manage to get features smaller than the wavelength of the light, 16nm is a real advance towards all day high performance computing and 10nm will come eventually and hopefully in their time period. I used to try and do things with assembler in the past and nowadays it is done so much better and with just a fraction of the effort, though that has meant I have got even more greedy for power!
10nmFinFET in 2015 is impressive indeed! It will be interesting to see how modeling and EDA views need to change to support the challenges of 10nm. And how general signoff will be impacted.
Thanks for the update Laurence. Adding an ARM Processors mention so the followers of that group get to see your message.
Andy
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