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Operating Systems forum

The latest forum discussions for all Arm technology relating to Operating Systems (OS)

272 questions

UEFI variables from UEFI shell 2 months ago
Servers and Cloud Computing forum

The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.

101 questions

RE: ArmRAL: Wrong usage of k0 in LDPC rate matching 5 months ago
SoC Design and Simulation forum

The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.

707 questions

In CHI how the Slave side is giving the L-Credits to the Master Side 4 days ago
SystemReady Forum

The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.

15 questions

RE: How to run ARM ACS 4 months ago
恩智浦汽车电子MCU讨论区博

4 questions

RE: [TRK-KEA64使用经验分享] 开箱体验亮瞎我的双眼 over 9 years ago

All questions in this Community

Not Answered
Saving processor state for power-down and resume 0
- Thumb
- Cortex-M4
4678 views

1 reply

Latest over 5 years ago
by 42Bastian Schick
Answered

interfacing STM32 F401re with mcp2515 0

3735 views

1 reply

Latest over 5 years ago
by Westonsupermare Pier
Not Answered

Pros and cons of activating cache in stm32F7 0

4003 views

0 replies

Started over 5 years ago
by Marzi
Answered

Static Call Graph Details in Keil IDE +1

5697 views

4 replies

Latest over 5 years ago
by MoAli
Answered
How to configure GIC in Cortex-R52 for FreeRTOS? 0
28834 views

2 replies

Latest over 5 years ago
by sska.73
Not Answered

making physical memory pages not cacheable (probabaly by modifying page table entry) 0

20365 views

0 replies

Started over 5 years ago
by Gol
Not Answered
Debug Connection Cause ExecutionTiming Problem on Second Core of Cortex A9 on Zynq 702 MPCore 0
- System on Chip (SoC)
- Cortex-A9
22319 views

3 replies

Latest over 5 years ago
by BurakSeker
Not Answered

reading data in http client application 0

1013 views

0 replies

Started over 5 years ago
by giomaca
Not Answered

NXP i.MXRT1064 Stack Corruption using FLEXCAN / LPUART / Systick Interrupts 0

1156 views

0 replies

Started over 5 years ago
by crevans
Not Answered
Store operations where the cache line is already cached (ACE protocol) 0
- AMBA
- AMBA 4
- AXI
- Interface
30668 views

9 replies

Latest over 5 years ago
by het
Not Answered

My code is not working if i change the address of flash memory , where the code can be loaded and if change the address back to the base address 0x80000000 then it works. Why? 0

24485 views

3 replies

Latest over 5 years ago
by Ronan Synnott
Not Answered

Build process failed in system canvas 0

18153 views

4 replies

Latest over 5 years ago
by vaiyawa
Not Answered

flush_cache_all() API consuming 200+ microseconds. 0

21320 views

4 replies

Latest over 5 years ago
by vaiyawa
Answered

UART Baud rate CMSIS Drivers 0

5628 views

6 replies

Latest over 5 years ago
by Robert McNamara
Answered
R5 vs A9 Performances +1
- Cortex-A9
- Cortex-R5
12956 views

9 replies

Latest over 5 years ago
by Poz1