V5.28, register watch

SVD file is correct, also SFR file contains correct base address (0x4000 0400) and offsets for registers SR (0x10) and EGR (0x14).

Proved via Memory Window:

So, µVision shows correct that SR instead of EGR has been written.

Wondering what is going wrong here...

Because stm32G0xx.h file is also correct:

typedef struct
{
  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
  __IO uint32_t PSC;         /*!< TIM prescaler register,                   Address offset: 0x28 */
  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
  __IO uint32_t OR1;         /*!< TIM option register,                      Address offset: 0x50 */
  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
  __IO uint32_t AF1;         /*!< TIM alternate function register 1,        Address offset: 0x60 */
  __IO uint32_t AF2;         /*!< TIM alternate function register 2,        Address offset: 0x64 */
  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */
} TIM_TypeDef;

#define PERIPH_BASE           (0x40000000UL)  /*!< Peripheral base address */
#define APBPERIPH_BASE        (PERIPH_BASE)
#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400UL)
#define TIM3                  ((TIM_TypeDef *) TIM3_BASE)

Checked asm output again...

;;;1156       TIM3->EGR  |=  TIM_EGR_UG;                                      // Force update generation (UG = 1)
0000b8  4608              MOV      r0,r1
0000ba  6940              LDR      r0,[r0,#0x14]
0000bc  2101              MOVS     r1,#1
0000be  4308              ORRS     r0,r0,r1
0000c0  4919              LDR      r1,|L20.296|
0000c2  6148              STR      r0,[r1,#0x14]

                  |L20.296|
                          DCD      0x40000400

At least checked device errata sheet as of Nov. 2018.
No matching issue there.

Juergen

How to properly post source code:

0x40000400: 80 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 01 00 00 00 00 00 00 00 03 00 00 00 
//......... CR1........ CR2........ SMCR....... DIER....... SR......... EGR........ CCMR1......

;;;1157       TIM3->DIER |= TIM_DIER_UIE;
0000b8  4608              MOV      r0,r1
0000ba  68c0              LDR      r0,[r0,#0xc]
0000bc  2101              MOVS     r1,#1
0000be  4308              ORRS     r0,r0,r1
0000c0  4922              LDR      r1,|L20.332|
0000c2  60c8              STR      r0,[r1,#0xc]
;;;1158       TIM3->SR   |= TIM_SR_UIF;              
0000c4  4608              MOV      r0,r1
0000c6  6900              LDR      r0,[r0,#0x10]
0000c8  2101              MOVS     r1,#1
0000ca  4308              ORRS     r0,r0,r1
0000cc  491f              LDR      r1,|L20.332|
0000ce  6108              STR      r0,[r1,#0x10]
;;;1159       TIM3->EGR  |= TIM_EGR_UG;
0000d0  4608              MOV      r0,r1
0000d2  6940              LDR      r0,[r0,#0x14]
0000d4  2101              MOVS     r1,#1
0000d6  4308              ORRS     r0,r0,r1
0000d8  491c              LDR      r1,|L20.332|
0000da  6148              STR      r0,[r1,#0x14]
;;;1160       TIM3->CCMR1 |= TIM_CCMR1_CC1S; 
0000dc  4608              MOV      r0,r1
0000de  6980              LDR      r0,[r0,#0x18]
0000e0  2103              MOVS     r1,#3
0000e2  4308              ORRS     r0,r0,r1
0000e4  4919              LDR      r1,|L20.332|
0000e6  6188              STR      r0,[r1,#0x18]

Result: Cannot write anything to TIM3->EGR.
Writes to TIM3->EGR are stored in SR.
Writes to DIER and CCMR1 are stored ok.
Maybe one can check the binary codes in asm-txt- output.
Juergen