I was getting a NOCP Usage Fault when my non-secure thread entered WIC sleep and a Secure Handler woke up the processor from WIC sleep.
I wasn't using any FPU code and I could not understand why the M33 was throwing a NOCP Usage Fault.
Luckily, I had access to IP and could see that I needed to set the NSACR and or clear the FPCCR ASPEN bit.
I bet there are other ways to do this unbeknownst to me, too.
I don't really understand the tradeoffs and could find no mention of when and why to set the various bits in the FPCCR in the UG or TRM.
So is there a good FPU programming reference anywhere that goes in depth on these scenarios?
Preferably one that talks about do's and don'ts with respect to Secure and Non Secure use.
I'll even take an M4 version if it exists.
Anyone have any insight on the correct way to use the FPU when sharing or not sharing between the Secure and Non-Secure states?
have you sent it in as a request to the support team?
I am not aware of any public documentation yet other than the product user guide.
soon, there will be more from the ecosystem partners.
Yes, I've forwarded my request to the support team.
What about the FPU for the M4? Is there a guide for that?
not to my knowledge. There are many libraries out there but I do not recall seeing any thing specific to the FPU. Have you checked out the book from Joseph?
Support team pointed me to an APP Note for v7M FPU stacking and context switching.
* App Note 298: Cortex-M4(F) Lazy Stacking and Context Switching
The support team confirmed my understanding and added more detail. I'm adding it in the thread for completeness.
Set | CPACR - C10/11 | CPACR_NS -C10/11 | NSACR - C10/11 | FPCCR.ASPEN | Result |
| A | 3 / 3 | 3 / 3 | 0 / 0 | 1 | NOCP Usage Fault |
| B | 3 / 3 | 0 / 0 | 0 / 0 | 1 | NOCP Usage Fault |
| C | 3 / 3 | 0 / 0 | 0 / 0 | 0 | Pass |
| D | 3 / 3 | 3 / 3 | 0 / 0 | 0 | Pass |
| E | 3 / 3 | 0 / 0 | 1 / 1 | 1 | Pass |
| F | 3 / 3 | 3 / 3 | 1 / 1 | 1 | Pass |
For sets A and B, where the NOCP Usage Fault occurs, `NSACR.CP10` is set to `0`, meaning that "Non-secure accesses to the Floating-point Extension generate a NOCP UsageFault" as described by D1.2.160 in the ArmARM.
For sets C and D, where the NOCP Usage Fault does not occur:
* `FPCCR.ASPEN` is set to `0`, meaning that executing an FP instruction has no
effect on `CONTROL.FPCA` as described by D1.2.81 in the ArmARM.
* Consequently, if `CONTROL.FPCA` is set to `0`, the "FP Extension is not
active", therefore the PE will not attempt to activate the FP extension.
* As a result, the fault does not occur.
For sets E and F, where the NOCP Usage Fault does not occur:
* `NSACR.CP10` is set to `1`, meaning that "Non-secure access to the
Floating-point Extension permitted" as described by D1.2.160 in the ArmARM.
* `FPCCR.ASPEN` is set to `1`, meaning that "Executing an FP instruction sets
CONTROL.FPCA to 1" as described by D1.2.81 in the ArmARM.
* When the PE attempts to `CONTROL.FPCA` to `1` upon executing a
floating-point instruction, it is allowed to do so.
Essentially, this comes down to the value of `NSACR.CP10`. If this value is set to `0`, the NOCP Usage Fault occurs.