Basically I want to provide delay of 15 clock cycles for writing and reading through axi4 bus .Is it possible?
Hi,
I cannot catch your intention.Please let us know it.Because latencies from "a read address valid" to "the corresponding read data responses" or from "a write address valid" to "the corresponding write response" would be unpredictable, is there any reason to add 15 cycle delay?Do you want AT LEAST 15 cycle delay?Do you design such a register slice by yourself?
Or do you want to by such a register slice?I think if you want to do so, you can only do it.What is the back ground of your question?
Best regards,Yasuhiko Koumoto.
Thank you so much for your replies.
I am using memory controller block(Xilinx) and I need to delay the read and writes for 15 clock cycles so that I can modify the data being written to memory. Xilinx uses AXI bus . So I was thinking to delay the data when present in AXI bus. I have tried to delay the reading and writing but it has corrupted the data. I need to know where can I delay the data in AXI bus. And I have not made register slice myself . I was using the inbuilt AXI register slice to do so.
Also as said by @jd_ if i try to delay the data between aw and w channel. Then how will my system behave under burst mode. Because according to me in burst mode aw channel will be utilised once. As consecutive addresses will be calculated by the axi itself.and therefore i wont be able provide delay to each data in burst mode.
All suggestions are welcome
Regards
Preet