Cortex-A7 pipeline is non-symmetric, what does this attribute mean?

I see that your question got already answered.

Actually, it's very odd to see the term "symmetric"/"non-symmetric" used in reference to a processor pipeline; the term "symmetric/non-symmetric" is sometimes used in multi-core processors to describe "identical/non-identical" cores. In the context of the processor pipeline, "symmetric pipelines" means that the symmetric pipeline can execute the same type of instruction in the same manner with the exact same latency. For example, some processors might have identical integer pipelines that execute with different latencies to save energy. Therefore, "non-symmetric" can mean that: (a) different integer pipelines have different latencies (highly unlikely here as I am not aware of any other commercial processor that implements this technique) or (b) some integer pipelines can only execute certain types of instructions similar to the dual-issue Cortex-M7 where the second integer pipeline can only execute a subset of integer instructions. I am not familiar with the A7 but the third integer pipeline means that is capable of issuing up to 3 integer instructions per cycle which is quite impressive but again this diagram is very basic and should not be used as a technical reference.

BTW, where did you find the "non-symmetric pipeline" reference. A search for the term on infocenter.arm.com reference 0 hits?

I see that your question got already answered.

Actually, it's very odd to see the term "symmetric"/"non-symmetric" used in reference to a processor pipeline; the term "symmetric/non-symmetric" is sometimes used in multi-core processors to describe "identical/non-identical" cores. In the context of the processor pipeline, "symmetric pipelines" means that the symmetric pipeline can execute the same type of instruction in the same manner with the exact same latency. For example, some processors might have identical integer pipelines that execute with different latencies to save energy. Therefore, "non-symmetric" can mean that: (a) different integer pipelines have different latencies (highly unlikely here as I am not aware of any other commercial processor that implements this technique) or (b) some integer pipelines can only execute certain types of instructions similar to the dual-issue Cortex-M7 where the second integer pipeline can only execute a subset of integer instructions. I am not familiar with the A7 but the third integer pipeline means that is capable of issuing up to 3 integer instructions per cycle which is quite impressive but again this diagram is very basic and should not be used as a technical reference.

BTW, where did you find the "non-symmetric pipeline" reference. A search for the term on infocenter.arm.com reference 0 hits?

Here is on old post that asks a similar question Cortex-a7 dual-issue? Surprisingly you can find out more details on the A7 arch from the GNU machine description file than ARM docs (I went through the whole A7 TRM and couldn't find a single reference to dual-issue apart from the disable bit in ACTLR)! The cortex-A7.md file has some insightfully comments that makes it a lot easier to decipher if you're not familiar with the syntax.

https://gcc.gnu.org/viewcvs/gcc/trunk/gcc/config/?sortby=date