I found the following code sequence in our code. Can I know if the following DSB(SY) guarantees that register access (#3) will be executed after contents of #1 flushed to DDR memory?
1: write value to DDR through write-combined memory mapping
3: direct register access
AFAIK, (2) does not guarantee the data is written to DDR, it might still be in the cache. If (3) is for example a DMA setup, you need to flush the cache before.
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