ARMV8 has number of exception levels as EL0 , EL1, EL2, EL3 .. How this is managed and what is the exact use case of the same ?
The four privilege levels of ARMv8 is really an extension and clarification of what was implemented in the later versions of ARMv7-A.
Most architectures, from any vendor, support some kind of "privilege" which is used by operating systems to protect the system from rogue our erroneous user software. The operating system runs at a privileged level which allows it access to protected features and the user software runs without this privilege so that it can be prevented from carrying out certain actions and accessing certain features.
In ARMv8, the four privilege levels extend this to provide support for virtualization and security. The levels behave like this:
PL0 - This is unprivileged and is used for executing user code under an OS or hypervisor
PL1 - This is privileged and is used for running an OS like Linux
PL2 - This has a higher level of privilege and can be used to run a hypervisor which takes control of the system and can host multiple "guest" operating systems
PL3 - This is the highest level off privilege and is used to control (and protect) access to the Secure world supported by TrustZone
So, you can see that each level has a distinct purpose and also that it is important that there is a hierarchy of privilege. For instance, system security would be compromised if PL3 was not the highest level of privilege. Likewise, hypervisor would not be able to control the action of guest operating systems if PL2 did not have a higher level than PL1. And so on.
Hope this helps.
Thanks for the reply.
This is applicable only for Cortex A alone or for both A & R series ?
It only really applies to Cortex-A at present.
- Most ARMv7-A processors (Cortex-A15, Cortex-A7 etc) support the four levels of privilege and the Virtualization Extensions. Sme of the earlier ones (e.g. Cortex-A9, Cortex-A5) do not support the Virtualization Extensions.
- ARMv7-R does not include the Virtualization Extensions so processors like Cortex-R4, Cortex-R5, Cortex-R7 do not support the extra privilege level.
- ARMv8-A includes everything I mentioned above (Cortex-A53, Cortex-A57 etc)
- The full details of ARMv8-R have not yet been released but we do know that it includes support for the Hypervisor Mode and the Virtualization Extensions allowing implementation of a full Type 1 Hypervisor.
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