Disable data prefetching in a Cortex-A53 running Android

Dear Experts,

I would like to disable the data prefetching engines of the L1 and L2 caches on a MediaTek-X20 board which includes a quad Cortex-A53 cluster and runs Android.

I have tried to include in the Linux kernel code (at kernel/init/main.c) a call to the following function:

static void __init disable_prefetch(void)
{
u64 value = 0;

printk("Manipulating data prefething register\n");

asm volatile("mrs %0, S3_1_C15_C2_0" : "=r" (value)); // read register
printk("Reading old S3_1_C15_C2_0 = %llx)\n", value);

asm volatile("msr S3_1_C15_C2_0, %0" :: "r" (value)); // write register

printk("Done manipulating data prefetching register\n");
}

However, the call to my function causes a kernel crash at booting. Instead, if I comment out the "write register" line, I am able to read the value of S3_1_C15_C2_0 during booting. 


Why am I not able to modify the content of S3_1_C15_C2_0?


Best,

d.

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