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Disable data prefetching in a Cortex-A53 running Android

DNovo

Dear Experts,

I would like to disable the data prefetching engines of the L1 and L2 caches on a MediaTek-X20 board which includes a quad Cortex-A53 cluster and runs Android.

I have tried to include in the Linux kernel code (at kernel/init/main.c) a call to the following function:

static void __init disable_prefetch(void)
{
u64 value = 0;

printk("Manipulating data prefething register\n");

asm volatile("mrs %0, S3_1_C15_C2_0" : "=r" (value)); // read register
printk("Reading old S3_1_C15_C2_0 = %llx)\n", value);

asm volatile("msr S3_1_C15_C2_0, %0" :: "r" (value)); // write register

printk("Done manipulating data prefetching register\n");
}

However, the call to my function causes a kernel crash at booting. Instead, if I comment out the "write register" line, I am able to read the value of S3_1_C15_C2_0 during booting. 


Why am I not able to modify the content of S3_1_C15_C2_0?


Best,

d.

Parents
  • 0 in reply to vstehle

    Dear vstehle,

    I've tried to gain access to the referred PMU event as follows:

    PAPI_add_event(EventSet, PAPI_NATIVE_MASK | 0xC2)

    but PAPI is not able to find any event higher than 0x0D... do you know any other way to access PMU events from the Linux/Android user-space?

    To give you more context, I had to add the following lines to the default Mediatek-X20 device tree file in order to gain access to the currently accessible PAPI events (i.e., PAPI_L1_ICM PAPI_L1_DCM PAPI_L1_DCA PAPI_L2_DCM PAPI_L2_DCA PAPI_LD_INS PAPI_SR_INS PAPI_BR_INS PAPI_TOT_INS PAPI_BR_MSP PAPI_TOT_CYC PAPI_TLB_DM PAPI_TLB_IM PAPI_HW_INT)

    + pmu_a53_0 {
    + compatible = "arm,armv8-pmuv3";
    + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
    + };
    +
    + pmu_a53_1 {
    + compatible = "arm,armv8-pmuv3";
    + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
    + };
    +
    + pmu_a72 {
    + compatible = "arm,armv8-pmuv3";
    + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-affinity = <&cpu8>, <&cpu9>;
    + };
    +

    Best,
    d.

Reply
  • 0 in reply to vstehle

    Dear vstehle,

    I've tried to gain access to the referred PMU event as follows:

    PAPI_add_event(EventSet, PAPI_NATIVE_MASK | 0xC2)

    but PAPI is not able to find any event higher than 0x0D... do you know any other way to access PMU events from the Linux/Android user-space?

    To give you more context, I had to add the following lines to the default Mediatek-X20 device tree file in order to gain access to the currently accessible PAPI events (i.e., PAPI_L1_ICM PAPI_L1_DCM PAPI_L1_DCA PAPI_L2_DCM PAPI_L2_DCA PAPI_LD_INS PAPI_SR_INS PAPI_BR_INS PAPI_TOT_INS PAPI_BR_MSP PAPI_TOT_CYC PAPI_TLB_DM PAPI_TLB_IM PAPI_HW_INT)

    + pmu_a53_0 {
    + compatible = "arm,armv8-pmuv3";
    + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
    + };
    +
    + pmu_a53_1 {
    + compatible = "arm,armv8-pmuv3";
    + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
    + };
    +
    + pmu_a72 {
    + compatible = "arm,armv8-pmuv3";
    + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-affinity = <&cpu8>, <&cpu9>;
    + };
    +

    Best,
    d.

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