for research reasons I'm working on the Cortex-A53 processor but I'm a bit confused about some aspects concerning RAM
My software needs to perform several writes to RAM, bypassing the store buffer and cache.
My first question is: how can I force writing directly to RAM? I thought about setting a range of addresses as NON-CACHEABLE but I did not understand how to do it.
The second question is: if I do two consecutive stores in the same address, both data arrive in RAM or the store buffer "blocks" it? is there a way to force the store buffer to "commit" the result after every single store? I read about the DSB and DMB instructions, but I'm not sure it's what I'm looking fo
Thanks for your help
To your first question, you need to set up your MMU to configure such memory region with non-cacheable attribute.
To your second question, yes, you can add DMB between these two stores to force each store is sent out
In this case, I think you actually need a DSB. DMB guarantee ordering between things before and after the barrier. A DSB causes the processor to wait for outstanding operations to actually finish. It (DSB) is roughly equivalent to drain write-buffer operation on older cores.
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