Hi AllI have two questions.Q1:is it ok that WVALID , WREADY and BVALID assert at the same cycle?Thanks!Q2: what is different between out of order and data interleaving ?Thanks!
WVALID, WREADY and BVALID can all be asserted in the same cycle, BUT NOT for the same transactions.
See the section in the AXI protocol titled "Dependencies between channel handshake signals (section A3.3.1 in the version E of the spec I am looking at). Here you will see that BVALID can only be asserted by the slave AFTER the final WVALID/WREADY channel handshake has completed, so definitely not at the same time.
"Interleaving" and "out of order" can only occur when using transactions with different IDs.
"Interleaving" means merging two different transaction ID data streams on consecutive cycles, making better use of available bus bandwidth if an earlier starting transaction cannot supply valid data on consecutive cycles. In AXI3 this could occur in both read and write transactions, but in AXI4 this is not supported for write transactions.
"Out of order" simply means that the transactions can end in a different order to that they were requested by the master. So for write transfers it would mean the B channel response for a later transaction ID being returned before the B channel response for an earlier transaction. Again this can only happen when those transactions are using different IDs (because how else would you know which transaction the response referred to if they used the same IDs).
WVALID, WREADY and BVALID can all be asserted in the same cycle, BUT NOT for the same transactions. See the section in the AXI protocol titled "Dependencies between channel handshake signals .
The write interleaving means a master will issue write data separately for one transaction. The out-of-order means a relationship between address PupilPath Login and data. On an AXI bus, IDs indicates the correspondence between addresses and data. Therefore, the order of addresses and data is independent.
Hi Tom Jacobs do the replies below answer your question? If so, please mark one of them as an accepted answer. Many thanks.
I prefer AXI lite for most situations. Just send the address with the data, and it can still support one data transfer per cycle. Back pressure is needed and I’m ok with some slaves supporting simultaneous reads and writes.
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