Arm is happy to announce the release of the next generation of AMBA 5 ACE5 and AXI5 protocols. A number of capabilities have been added over the prior AMBA 4 generation to align with AMBA 5 CHI. The protocols have been implemented in Arm’s latest technology including DynamIQ processers such as Cortex-A75 and Cortex-A55 along with the CoreLink CMN-600 Coherent Mesh Network.
To recap, here are the 3 main protocols included within the ACE and AXI specification:
As mentioned, the new AMBA 5 ACE5, ACE5-Lite and AXI5 align with CHI to provide a number of performance and reliability capabilities including Atomics, Cache Stashing and RAS signaling. The table below provides a high-level overview of which enhancements are available for the different protocols and the following CHI release blog post describes the features and benefits in more depth.
Introducing new AMBA 5 CHI protocol enhancements | Specification now available blog post
To find out more details about the new protocols, please see the specification which is now available for download on the Arm Developer AMBA 5 website.
Thanks for the great summary and congratulations on the launch, Jeff Defilippi. Our team has enjoyed the collaboration with Arm on this and past Arm AMBA specifications. We're excited to have support for these new specs as you launch them, with early adopter cusotmer success. My short blog introduces our AMBA 5 AXI5/ACE5 solutions: https://community.arm.com/processors/b/blog/posts/synopsys-supports-new-arm-amba-5-axi5-ace5-protocols.