In this post, we look at how to write, compile, and run a simple RTX app on the custom Cortex-M33 platform that we built in the first post. We also explore the Fast Models Trace plugins to trouble shoot any issues that we might face while running our application.
You need to download the following:
Here is the code for the simple timer app:
#include "cmsis_os2.h" #include <stdio.h> void periodicTimerCallback(void *argument); void oneShotTimerCallback(void *argument); void app_main (void *argument); osTimerId_t tidPeriodic; osTimerId_t tidOneShot; void periodicTimerCallback(void *argument) { printf("Periodic Timer hit\n"); } void oneShotTimerCallback(void *argument) { printf("One shot Timer hit\n"); } void app_main (void *argument) { tidPeriodic = osTimerNew(periodicTimerCallback, osTimerPeriodic, NULL, NULL); tidOneShot = osTimerNew(oneShotTimerCallback, osTimerOnce, NULL, NULL); osTimerStart(tidPeriodic, 100); osTimerStart(tidOneShot, 2000); while(1); } int main (void) { osKernelInitialize(); osThreadNew(app_main, NULL, NULL); osKernelStart(); }
Code in the previous example is mostly self-explanatory. We do the following:
Then use the following Makefile to compile the previous application:
CMSIS_HOME=<PATH-TO-CMSIS_5-REPO> CC=armclang ASM=armasm LNK=armlink INC=-I${CMSIS_HOME}/CMSIS/RTOS2/Include -I${CMSIS_HOME}/CMSIS/RTOS2/RTX/Include -I${CMSIS_HOME}/CMSIS/RTOS2/RTX/Source -I${CMSIS_HOME}/Device/ARM/ARMCM33/Include -I${CMSIS_HOME}/CMSIS/Core/Include -I./app/ -I./RTE/CMSIS -I./RTE/_Simulation/ CFLAGS=--target=arm-arm-none-eabi -g -O0 -xc -std=c99 -D_RTE_ -march=armv8-m.main -mcpu=cortex-m33+nodsp+nofp16 -mfpu=none -mfloat-abi=soft -mthumb -DARMCM33 CFLAGS+=${INC} ASMFLAGS=--target=arm-arm-none-eabi -g -D_RTE_ -march=armv8-m.main -mcpu=cortex-m33+nodsp+nofp16 -mfpu=none -mfloat-abi=soft -mthumb -DARMCM33 LDFLAGS=--scatter ./RTE/Device/AEMv8M_mainline.sct --entry=Reset_Handler SRC=$(wildcard ${CMSIS_HOME}/CMSIS/RTOS2/RTX/Source/*.c) \ $(wildcard ${CMSIS_HOME}/CMSIS/RTOS2/Source/os_systick.c) \ $(wildcard ./RTE/CMSIS/*.c) \ $(wildcard ./RTE/Device/*.c) \ $(wildcard ./app/*.c) SRC_S=$(wildcard ./RTE/Device/*.S) OBJ=$(SRC:.c=.o) OBJ_S=$(SRC_S:.S=.o) %.o: %.S $(CC) -o $@ $(ASMFLAGS) -c $< test.axf: $(OBJ) $(OBJ_S) $(LNK) -o $@ $(LDFLAGS) $^ clean: find ${CMSIS_HOME} -name "*.o" -exec rm -rf {} \; find ./ -name "*.o" -exec rm -rf {} \; rm test.axf
In the previous Makefile, update CMSIS_HOME path to point to the CMSIS_5 directory of the CMSIS repo that you cloned from the github link given previously.
We use some special compiler and assembler flags like "-march" and "-mcpu" to generate image that runs on those cpus. In the previous example, we specify target architecture as "armv8-m.main" and CPU as "Cortex-M33+nodsp+nofp16". So, the compiler knows that the binary generated should be compatible to run on ARMv8M mainline Cortex-M33 CPU that does not support DSP or FP16.
Another interesting file to look at is the scatter file used during linking of the application. Let us have a look at the scatter file:
LR_IROM1 0x00000000 0x00200000 { ; load region size_region ER_IROM1 0x00000000 0x00200000 { ; load address = execution address *.o (.vectors, +First) * (InRoot$$Sections) .ANY (+RO) .ANY (+XO) } RW_IRAM1 0x20000000 0x00020000 { .ANY (+RW +ZI) } } LR_IROM2 0x00200000 0x00200000 { ER_IROM2 0x00200000 0x00200000 { ; load address = execution address .ANY (+RO) } }
Scatter files help define one or more load regions in memory. Each load region contains one or more execution regions. Linker uses the information in the scatter file to generate the elf file. Using the scatter file you can control where the linker places different parts of your test image for your particular target. Read here to know more about scatter files.
Then run "make". On completion, "test.axf" is created. This is the final app that we can now run on the Cortex-M33 FM platform that we created in the post 1.
We can run the following command to execute our RTX app on the Fast Models Cortex-M33 platform:
$ ls -l total 316 drwxr-x--- 3 navkha01 navkha01 4096 Dec 24 11:36 Linux64-Release-GCC-6.4 -rw-r----- 1 navkha01 navkha01 586 Dec 24 11:34 MyTopComponent.lisa -rw-r----- 1 navkha01 navkha01 292911 Dec 24 11:34 MyTopComponent.sgcanvas -rw-r----- 1 navkha01 navkha01 7109 Dec 24 11:36 MyTopComponent.sgproj
$ cd Linux64-Release-GCC-6.4/ $ ls -l total 51832 -rw-r----- 1 navkha01 navkha01 14332 Dec 24 11:36 MyTopComponent_Linux64-Release-GCC-6.4_Makefile.sg drwxr-x--- 2 navkha01 navkha01 36864 Dec 24 11:36 gen -rwxr-x--- 1 navkha01 navkha01 7255368 Dec 24 11:36 isim_system -rw-rw-r-- 1 navkha01 navkha01 1588016 Apr 18 2019 libMAXCOREInitSimulationEngine.3.so -rw-r--r-- 1 navkha01 navkha01 1221177 Jan 26 2017 libSDL2-2.0.so.0.4.0 -rw-rw-r-- 1 navkha01 navkha01 39562768 Dec 10 18:23 libarmctmodel.so -rw-rw-r-- 1 navkha01 navkha01 68176 Nov 18 20:37 libarmfastmodelsanalytics.1.1.0.so -rw-r----- 1 navkha01 navkha01 1712236 Dec 24 11:36 libisim_system.a -rw-r--r-- 1 navkha01 navkha01 1260624 May 15 2018 librui_5.2.0.x64.so -rw-r----- 1 navkha01 navkha01 25664 Dec 24 11:36 libscx-MyTopComponent-Linux64-Release-GCC-6.4.a -rw-r----- 1 navkha01 navkha01 311056 Dec 24 11:36 libscx.a
$ ./isim_system -a /work/tests/rtx/final_app/fm_rtx_app/test.axf Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit One shot Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit Periodic Timer hit ^C Stopping simulation... Info: /OSCI/SystemC: Simulation stopped by user.
At times, while running your application on Fast Models platform, you do not get the desired output. You can use trace based plugins to get some insight into the execution during run time.
There are three main Trace-related plugins that you can use to get insights into the platform execution:
Let us have a quick look at these plugins and how to use them.
Tarmac is textual trace output that all core models in Fast Models support. All FM core models, generate traces that when processed through Tarmac Trace plugin print information related to the current Execution state of the core. Tarmac Trace plugin processes the incoming Model Trace Interface (MTI) events and produces a textual output that prints to console (or log file) for each core that is executing instructions.
Use the following additional option to load Tarmac Trace plugin when executing your platform:
$./isim_system -a /work/tests/rtx/final_app/fm_rtx_app/test.axf --plugin ${PVLIB_HOME}/plugins/Linux64_GCC-6.4/TarmacTrace.so
In the output, you can see each instruction that is executed along with the General Purpose or System Registers that are effected by the execution of that instruction. On loading the TarmacTrace plugin, we get Cortex-M33's execution state output as:
Attaching the Tarmac trace to component MyTopComponent.armcortexm33ct. 0 clk E DebugEvent_HaltingDebugState 00000000 0 clk R cpsr 01000000 0 clk R DHCSR 03100000 0 clk R DEMCR 00100000 0 clk R DSCSR 00030000 0 clk R FPDSCR_S 00000000 0 clk R DAUTHSTATUS 000000ea 0 clk R FPDSCR_NS 00000000 0 clk R r0 00000000 0 clk R r1 00000000 0 clk R r2 00000000 0 clk R r3 00000000 0 clk R r4 00000000 0 clk R r5 00000000 0 clk R r6 00000000 0 clk R r7 00000000 0 clk R r8 00000000 0 clk R r9 00000000 0 clk R r10 00000000 0 clk R r11 00000000 0 clk R r12 00000000 0 clk R s0 00000000 0 clk R s1 00000000 0 clk R s2 00000000 0 clk R s3 00000000 0 clk R s4 00000000 0 clk R s5 00000000 0 clk R s6 00000000 0 clk R s7 00000000 0 clk R s8 00000000 0 clk R s9 00000000 0 clk R s10 00000000 0 clk R s11 00000000 0 clk R s12 00000000 0 clk R s13 00000000 0 clk R s14 00000000 0 clk R s15 00000000 0 clk R s16 00000000 0 clk R s17 00000000 0 clk R s18 00000000 0 clk R s19 00000000 0 clk R s20 00000000 0 clk R s21 00000000 0 clk R s22 00000000 0 clk R s23 00000000 0 clk R s24 00000000 0 clk R s25 00000000 0 clk R s26 00000000 0 clk R s27 00000000 0 clk R s28 00000000 0 clk R s29 00000000 0 clk R s30 00000000 0 clk R s31 00000000 0 clk R fpexc 40000000 0 clk R DHCSR 03000000 0 clk R DAUTHSTATUS 000000aa 0 clk E 0020004c 00000001 CoreEvent_RESET 0 clk R r13_main_s 00003fc0 0 clk R MSP_S 00003fc0 1 clk IT (1) 0020004c f601fb6a T thread_s : BL {pc}-0x1fe928 ; 0x1724 1 clk R r14 00200051 2 clk IT (2) 00001724 f2400000 T thread_s : MOVW r0,#0 2 clk R r0 00000000 3 clk IT (3) 00001728 f2c00000 T thread_s : MOVT r0,#0 3 clk R r0 00000000 4 clk IT (4) 0000172c f64e5108 T thread_s : MOV r1,#0xed08 4 clk R r1 0000ed08 5 clk IT (5) 00001730 f2ce0100 T thread_s : MOVT r1,#0xe000 5 clk R r1 e000ed08 6 clk IT (6) 00001734 6008 T thread_s : STR r0,[r1,#0] 6 clk MW4 e000ed08 00000000 6 clk R VTOR_S 00000000 7 clk IT (7) 00001736 f2400010 T thread_s : MOVW r0,#0x10 7 clk R r0 00000010 8 clk IT (8) 0000173a f2c20000 T thread_s : MOVT r0,#0x2000 8 clk R r0 20000010 9 clk IT (9) 0000173e f6470140 T thread_s : MOV r1,#0x7840 9 clk R r1 00007840 10 clk IT (10) 00001742 f2c0117d T thread_s : MOVT r1,#0x17d 10 clk R r1 017d7840 11 clk IT (11) 00001746 6001 T thread_s : STR r1,[r0,#0] 11 clk MW4 20000010 017d7840 12 clk IT (12) 00001748 4770 T thread_s : BX lr 12 clk R cpsr 01000000 13 clk IT (13) 00200050 f600f836 T thread_s : BL {pc}-0x1fff90 ; 0xc0 13 clk R r14 00200055 14 clk IT (14) 000000c0 f000f802 T thread_s : BL {pc}+8 ; 0xc8 14 clk R r14 000000c5 15 clk IT (15) 000000c8 a00a T thread_s : ADR r0,{pc}+0x2c ; 0xf4 15 clk R r0 000000f4 16 clk IT (16) 000000ca e8900c00 T thread_s : LDM r0,{r10,r11} 16 clk MR4 000000f4 00003ecc 16 clk MR4 000000f8 00003eec 16 clk R r10 00003ecc 16 clk R r11 00003eec 17 clk IT (17) 000000ce 4482 T thread_s : ADD r10,r10,r0 17 clk R r10 00003fc0 18 clk IT (18) 000000d0 4483 T thread_s : ADD r11,r11,r0 18 clk R r11 00003fe0 19 clk IT (19) 000000d2 f1aa0701 T thread_s : SUB r7,r10,#1 19 clk R r7 00003fbf 20 clk IT (20) 000000d6 45da T thread_s : CMP r10,r11 20 clk R cpsr 81000000 21 clk IT (21) 000000d8 d101 T thread_s : BNE {pc}+6 ; 0xde 22 clk IT (22) 000000de f2af0e09 T thread_s : ADR lr,{pc}-7 ; 0xd7 22 clk R r14 000000d7 23 clk IT (23) 000000e2 e8ba000f T thread_s : LDM r10!,{r0-r3} 23 clk MR4 00003fc0 00003fe0 23 clk MR4 00003fc4 20000000 23 clk MR4 00003fc8 00000160 23 clk MR4 00003fcc 000000fc 23 clk R r0 00003fe0 23 clk R r1 20000000 23 clk R r2 00000160 23 clk R r3 000000fc 23 clk R r10 00003fd0 24 clk IT (24) 000000e6 f0130f01 T thread_s : TST r3,#1 24 clk R cpsr 41000000 25 clk IT (25) 000000ea bf18 T thread_s : IT NE 25 clk R cpsr 41001800 26 clk IS (26) 000000ec 1afb T thread_s : SUBNE r3,r7,r3 26 clk R cpsr 41000000 27 clk IT (27) 000000ee f0430301 T thread_s : ORR r3,r3,#1 27 clk R r3 000000fd 28 clk IT (28) 000000f2 4718 T thread_s : BX r3 28 clk R cpsr 41000000 29 clk IT (29) 000000fc 440a T thread_s : ADD r2,r2,r1 29 clk R r2 20000160 30 clk IT (30) 000000fe f8104b01 T thread_s : LDRB r4,[r0],#1 30 clk MR1 00003fe0 01 30 clk R r0 00003fe1 30 clk R r4 00000001 31 clk IT (31) 00000102 f014050f T thread_s : ANDS r5,r4,#0xf 31 clk R r5 00000001 31 clk R cpsr 01000000 32 clk IT (32) 00000106 bf08 T thread_s : IT EQ 32 clk R cpsr 01000800 33 clk IS (33) 00000108 f8105b01 T thread_s : LDRBEQ r5,[r0],#1 33 clk R cpsr 01000000 34 clk IT (34) 0000010c 0924 T thread_s : LSRS r4,r4,#4 34 clk R r4 00000000 34 clk R cpsr 41000000 35 clk IT (35) 0000010e bf08 T thread_s : IT EQ 35 clk R cpsr 41000800 36 clk IT (36) 00000110 f8104b01 T thread_s : LDRBEQ r4,[r0],#1 36 clk MR1 00003fe1 11 36 clk R r0 00003fe2 36 clk R r4 00000011 36 clk R cpsr 41000000 .... ....
All Fast Model components publish large number of MTI trace sources that can be utilized to extract Execution state of these components during run time. For example, all FM cores publish SYSREG_UPDATE32 and SYSREG_UPDATE64 traces that have events triggered every time any System register gets updated in the core. In a large system, there can be thousands of such trace sources being published. As an end user, you can list all the trace sources published by your platform using ListTraceSource plugin.
Use the following command to additionally load ListTraceSource plugin:
$./isim_system --plugin $PVLIB_HOME/plugins/Linux64_GCC-6.4/ListTraceSources.so
Above command prints all the trace sources published by each component in the platform. Example output for our custom Cortex-M33 platform is as follows:
Component (0) providing trace: MyTopComponent (MyTopComponent, ) ============================================================================= Component is of type "MyTopComponent" Version is "" #Sources: 0 Component (1) providing trace: MyTopComponent.armcortexm33ct (ARM_Cortex-M33, 11.9.47) ============================================================================= Component is of type "ARM_Cortex-M33" Version is "11.9.47" #Sources: 205 Source ASYNC_MEMORY_FAULT (Context ID Register write.) Field FAULT type:MTI_UNSIGNED_INT size:4 (Fault status) Field PADDR type:MTI_UNSIGNED_INT size:4 (Physical Address (or 0 if unavailable)) Source ATOMIC_END_ACCESS (Bus trace access for atomics.) Field ADDR type:MTI_UNSIGNED_INT size:8 (The virtual address of the access.) Field PADDR type:MTI_UNSIGNED_INT size:8 (The physical address of the access.) Field NSDESC type:MTI_UNSIGNED_INT size:1 (The security state of the access.) Field PRIV type:MTI_BOOL size:1 (Is this a privileged access?) Field ATTR type:MTI_UNSIGNED_INT size:4 (Transaction Attributes: [11] Non-secure, [10] Privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer memory attributes, [3:0] inner memory attributes ([7]/[3] Allocate (Other Allocate when read), [6]/[2] Allocate (Other Allocate when write), [5]/[1] Modifiable, [4]/[0] Bufferable). All other bits are implementation defined) Field OPERATION type:MTI_ENUM size:1 (Operation type) 0x0 = ADD 0x1 = BIC 0x2 = EOR 0x3 = ORR 0x4 = SMAX 0x5 = SMIN 0x6 = UMAX 0x7 = UMIN 0x8 = SWP 0x9 = CAS 0xa = NON Field OPERAND_VALUE type:MTI_UNSIGNED_INT size:0 max_size:16 (Operation's operand) Field COMPARE_VALUE type:MTI_UNSIGNED_INT size:0 max_size:16 (Compare value for CAS) Field LOAD_VALUE type:MTI_UNSIGNED_INT size:0 max_size:16 (Loaded values) Field ACCESS_FAIL type:MTI_BOOL size:1 (Memory access failed) Source ATOMIC_START_ACCESS (Bus trace access for atomics.) Field ADDR type:MTI_UNSIGNED_INT size:8 (The virtual address of the access.) Field PADDR type:MTI_UNSIGNED_INT size:8 (The physical address of the access.) Field NSDESC type:MTI_UNSIGNED_INT size:1 (The security state of the access.) Field PRIV type:MTI_BOOL size:1 (Is this a privileged access?) Field ATTR type:MTI_UNSIGNED_INT size:4 (Transaction Attributes: [11] Non-secure, [10] Privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer memory attributes, [3:0] inner memory attributes ([7]/[3] Allocate (Other Allocate when read), [6]/[2] Allocate (Other Allocate when write), [5]/[1] Modifiable, [4]/[0] Bufferable). All other bits are implementation defined) Field OPERATION type:MTI_ENUM size:1 (Operation type) 0x0 = ADD 0x1 = BIC 0x2 = EOR 0x3 = ORR 0x4 = SMAX 0x5 = SMIN 0x6 = UMAX 0x7 = UMIN 0x8 = SWP 0x9 = CAS 0xa = NON Field OPERAND_VALUE type:MTI_UNSIGNED_INT size:0 max_size:16 (Operation's operand) Field COMPARE_VALUE type:MTI_UNSIGNED_INT size:0 max_size:16 (Compare value for CAS) Source ArchMsg.Warning.TarmacReconstructor (Unexpected event happened during Tarmac reconstruction DISPLAY Unexpected event %{REASON}) Field REASON type:MTI_STRING size:0 max_size:255 (Reason) Source ArchMsg.Warning.Unpredictably Indexed PM Event Register (DISPLAY Event %{IsDirect:(Selector value|Register)} %{SEL} is >= %{N}) Field SEL type:MTI_UNSIGNED_INT size:4 (Selector) Field IsDirect type:MTI_UNSIGNED_INT size:1 (Direct Access rather than indirect) Field N type:MTI_UNSIGNED_INT size:4 (Number of Accessible Registers) Source ArchMsg.Warning.branch_to_unaligned_address (DISPLAY Branch to unaligned_address %{ADDR}) Field ADDR type:MTI_UNSIGNED_INT size:8 (Unaligned branch address) Source ArchMsg.Warning.dap_csw_bad_size (A write to CM3DAP CSW has an invalid size field. DISPLAY Write %{DATA} to CM3DAP CSW has invalid size field ) Field DATA type:MTI_UNSIGNED_INT size:4 (bits[2:0] are size) Source ArchMsg.Warning.dcimvac_matches_watchpoint (DISPLAY Watchpoints matching an AArch32 DCIMVA are implementation defined) Source ArchMsg.Warning.decode_fieldmismatch (DISPLAY Instruction is unpredictable with different fields %{FIELD1} and %{FIELD2}) Field FIELD1 type:MTI_ENUM size:4 (Field name) 0x0 = UNUSED_FIELDID 0x1 = RN 0x2 = RM 0x3 = RA 0x4 = RS 0x5 = RD 0x6 = RDLO 0x7 = RDHI 0x8 = RT 0x9 = RT2 0xa = MSB 0xb = LSB 0xc = WIDTHM1 0xd = IMM12 0xe = W 0xf = P 0x10 = MASK 0x11 = SZ Field FIELD2 type:MTI_ENUM size:4 (Field name) 0x0 = UNUSED_FIELDID 0x1 = RN 0x2 = RM 0x3 = RA 0x4 = RS 0x5 = RD 0x6 = RDLO 0x7 = RDHI 0x8 = RT 0x9 = RT2 0xa = MSB 0xb = LSB 0xc = WIDTHM1 0xd = IMM12 0xe = W 0xf = P 0x10 = MASK 0x11 = SZ ..... ..... .....
You can use GenericTrace plugin to print basic information for each individual event that you are interested in. For example, let us say that you are interested in all the "EXCEPTION" events that happen in the core during execution of your workload. You can use the following command to filter "EXCEPTION" related events by using the GenericTrace plugin:
$./isim_system -a /work/tests/rtx/final_app/fm_rtx_app/test.axf --plugin $PVLIB_HOME/plugins/Linux64_GCC-6.4/GenericTrace.so -C TRACE.GenericTrace.trace-sources="*EXCEPTION*"
GenericTrace: model version is 1.0 EXCEPTION_START: NS=SEC EXCEPTION_START: NS=SEC EXCEPTION_END: NS=SEC EXCEPTION_END: NS=SEC EXCEPTION_START: NS=SEC EXCEPTION_VECTOR_FETCH: CORE_NUM=0x00 VADDR=0x00000000 DATA=0x00003fc0 RESPONSE=OK EXCEPTION_ENTRY: PC=0x0020004c VECTOR=RESET EXCEPTION: PC=0x0020004c ISET=Thumb LR=0xffffffff TARGET_PC=0x0020004c VECTOR=RESET TARGET_ISET=Thumb CORE_NUM=0x00 NS=SEC EXCEPTION_END: NS=SEC EXCEPTION_RAISE EXCEPTION_START: NS=SEC EXCEPTION_ENTRY: PC=0x00001a04 VECTOR=SVCALL EXCEPTION_VECTOR_FETCH: CORE_NUM=0x00 VADDR=0x0000002c DATA=0x002000b5 RESPONSE=OK INFO_EXCEPTION_REASON: PHASE=ACTIVATE REASONS=UNSPECIFIED PC=0x00001a04 VECTOR=SVCALL FaultCause=NO_FSR_BIT SecurityState=SECURE EXCEPTION: PC=0x00001a04 ISET=Thumb LR=0xfffffff9 TARGET_PC=0x002000b4 VECTOR=SVCALL TARGET_ISET=Thumb CORE_NUM=0x00 NS=SEC EXCEPTION_END: NS=SEC EXCEPTION_RAISE EXCEPTION_START: NS=SEC EXCEPTION_RETURN_PREBRANCH EXCEPTION_RETURN: PC=0x002000e6 ISET=Thumb INST_COUNT=0x0000000000000000 CORE_NUM=0x00 INFO_EXCEPTION_REASON: PHASE=DEACTIVATE REASONS=UNSPECIFIED PC=0x002000e6 VECTOR=SVCALL FaultCause=NO_FSR_BIT SecurityState=SECURE EXCEPTION_END: NS=SEC EXCEPTION_RAISE EXCEPTION_START: NS=SEC EXCEPTION_ENTRY: PC=0x00201994 VECTOR=SVCALL EXCEPTION_VECTOR_FETCH: CORE_NUM=0x00 VADDR=0x0000002c DATA=0x002000b5 RESPONSE=OK INFO_EXCEPTION_REASON: PHASE=ACTIVATE REASONS=UNSPECIFIED PC=0x00201994 VECTOR=SVCALL FaultCause=NO_FSR_BIT SecurityState=SECURE EXCEPTION: PC=0x00201994 ISET=Thumb LR=0xfffffff9 TARGET_PC=0x002000b4 VECTOR=SVCALL TARGET_ISET=Thumb CORE_NUM=0x00 NS=SEC EXCEPTION_END: NS=SEC EXCEPTION_RAISE EXCEPTION_START: NS=SEC EXCEPTION_RETURN_PREBRANCH EXCEPTION_RETURN: PC=0x002000e6 ISET=Thumb INST_COUNT=0x0000000000000000 CORE_NUM=0x00 INFO_EXCEPTION_REASON: PHASE=DEACTIVATE REASONS=UNSPECIFIED PC=0x002000e6 VECTOR=SVCALL FaultCause=NO_FSR_BIT SecurityState=SECURE EXCEPTION_END: NS=SEC EXCEPTION_RAISE EXCEPTION_START: NS=SEC EXCEPTION_ENTRY: PC=0x00201994 VECTOR=SVCALL EXCEPTION_VECTOR_FETCH: CORE_NUM=0x00 VADDR=0x0000002c DATA=0x002000b5 RESPONSE=OK INFO_EXCEPTION_REASON: PHASE=ACTIVATE REASONS=UNSPECIFIED PC=0x00201994 VECTOR=SVCALL FaultCause=NO_FSR_BIT SecurityState=SECURE EXCEPTION: PC=0x00201994 ISET=Thumb LR=0xfffffff9 TARGET_PC=0x002000b4 VECTOR=SVCALL TARGET_ISET=Thumb CORE_NUM=0x00 NS=SEC EXCEPTION_END: NS=SEC EXCEPTION_RAISE EXCEPTION_START: NS=SEC EXCEPTION_RETURN_PREBRANCH EXCEPTION_RETURN: PC=0x002000e6 ISET=Thumb INST_COUNT=0x0000000000000000 CORE_NUM=0x00 INFO_EXCEPTION_REASON: PHASE=DEACTIVATE REASONS=UNSPECIFIED PC=0x002000e6 VECTOR=SVCALL FaultCause=NO_FSR_BIT SecurityState=SECURE EXCEPTION_END: NS=SE
You can explore more such trace source events and then use GenericTrace to filter these events.
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