Architectures and Processors blog

With the arrival of Windows RT and the opening of Microsoft App Store, you can now develop Windows Store Apps on ARM platforms and make them available to 200+ markets via the Microsoft App Store. If you…

Last month Google and Samsung released the first commercially available product using the ARM® Cortex™-A15 SoC design: the new Series 3 Chromebook. Not only does the Chromebook have the new…

I would like to share some news around one of the products we recently released, the V2P-CA15x2_A7x3.  This is a new member of the Versatile ™ Express CoreTile family and is the first ARM big…

The introduction of a new architecture as significant as ARMv8, or AArch 64, requires careful consideration of the impact to existing software! The good news is, the new architecture is compatible with…

The ARM architecture has been used for many years in mobile phones and electronic devices, but it is only relatively recently that the architecture has diversified into being used in laptops, tablets and…

Debugging and optimizing software is always a demanding job.  As today's  systems become more complex the task of providing a suitable debug and  trace solution becomes increasingly challenging - yet it…

When writing code for Neon, you may find that sometimes, the data in your registers are not quite in the correct format for your algorithm. We explore this in further detail here.

Page colouring is sometimes used as an optimization but as a result of the cache architecture some ARMv6 processors actually require the allocator use page colouring. This article will explain why the…

This article is the first of a series on Arm fundamentals that will introduce various topics to help you get more familiar with the Arm architecture.

This post goes into the juicy bits of what memory access ordering actually means and how this is handled in the Arm architecture.

The modern web is built primarily from three technologies: HTML, CSS and JavaScript. It is JavaScript that drives the interactive web; slow JavaScript means slow web pages. So today, a huge amount of effort…

In my first blog, we examined gave the historical context of the instruction set battles of ARM and x86, covering the RISC-CISC Wars in the PrePC Era and the PC Era. This blog covers Round 3, the PostPC…

This two-part blog gives a historical perspective on the ARM vs. 80x86 instruction set competition for three eras: PrePC (late 1970s/early 1980s), PC (mid 1980s to mid 2000s), and PostPC (late 2000s onward…

The 2010 ARM Technology Conference (Techcon) is taking place in Santa Clara next week. A large number of companies will be presenting their solutions to support development and optimization of products…

Wow it's that time again; our 4th release of Ubuntu on ARM is upon us. In the past we have provided a Freescale iMX51 image, a Marvell Dove image and a TI OMAP 3 image for Beagle Boards. This cycle…

This post is part of a series:Condition Codes 1: Condition Flags and CodesCondition Codes 2: Conditional ExecutionCondition Codes 3: Conditional Execution in Thumb-2Condition Codes 4: Floating-Point Comparison…

In the last article, I explained how to modify SWP code to make use of compiler intrinsics.  Using intrinsics hides the underlying detail needed to use the load and store exclusive instructions (LDREX…

Before ARMv6, the main synchronisation mechanism was the SWP instruction. SWP has two aspects, in a uniprocessor system it allows the read and write operations not to be interrupted between them.   In…

My previous post provided an introduction to memory access ordering. It did not however, provide any solution to the problem. This post covers barrier use within the Linux kernel.

In this post, I will be introducing a few concepts and explain the reasons behind them. In future posts, I will follow up with practical examples.

Version 3.6.0 of Valgrind was released a couple of weeks ago. The largest change this release is the addition of support for Linux running on ARM. Learn more about the release in this blog.