Architectures and Processors blog

Wow it's that time again; our 4th release of Ubuntu on ARM is upon us. In the past we have provided a Freescale iMX51 image, a Marvell Dove image and a TI OMAP 3 image for Beagle Boards. This cycle…

This post is part of a series:Condition Codes 1: Condition Flags and CodesCondition Codes 2: Conditional ExecutionCondition Codes 3: Conditional Execution in Thumb-2Condition Codes 4: Floating-Point Comparison…

In the last article, I explained how to modify SWP code to make use of compiler intrinsics.  Using intrinsics hides the underlying detail needed to use the load and store exclusive instructions (LDREX…

Before ARMv6, the main synchronisation mechanism was the SWP instruction. SWP has two aspects, in a uniprocessor system it allows the read and write operations not to be interrupted between them.   In…

My previous post provided an introduction to memory access ordering. It did not however, provide any solution to the problem. This post covers barrier use within the Linux kernel.

In this post, I will be introducing a few concepts and explain the reasons behind them. In future posts, I will follow up with practical examples.

Version 3.6.0 of Valgrind was released a couple of weeks ago. The largest change this release is the addition of support for Linux running on ARM. Learn more about the release in this blog.

This article introduces the shifting operations provided by Neon, and shows how they can be used to convert image data between commonly used color depths.

Armv8 deprecates the use of the it instruction to make anything other than a single 16-bit instruction conditional. This affects many of the examples in this post.

It was always about the code (and where it would be used!) When I was a software developer I would often find that the project team I was in would try to guess how many devices the code would eventually…

This blog is a tutorial on detecting overflow from MUL.

In this post, we will look at how to efficiently multiply four-by-four matrices together, an operation frequently used in the world of 3D graphics.

This post will show you how we can deal with these limitations and how the latest revision of the Arm architecture (Armv7) provides a simple and efficient solution.

Arm implements conditional execution using a set of flags which store state information about a previous operation. in this post I shed some light on the operation of these flags.

In this post, we deal with an often encountered problem: input data that is not a multiple of the length of the vectors you want to process.

Sitting in the airport at the end of a week's business trip to the US, I reflected back on the week.  It turned out that my colleague on this trip has an even worse sense of direction than myself.…

This is the first part of a series on how to write SIMD code for Neon using assembly language. It covers getting started with Neon, using it efficiently, and more.

Ideally caches act as magic make-it-go-faster logic sitting between processor cores and memory banks. But there are cases where cache behaviour must be considered to get the desired result.

This post aims to provide a simple introduction to Arm assembly language.

Once you move beyond short sequences of optimised Arm assembler, the next likely step will be to managing more complex, optimised routines using macros and functions.

One of the key challenges faced by the semiconductor industry today is balancing the growing, yet conflicting demand for mobile devices featuring both high performance and long battery life. Last week…