Architectures and Processors blog

Having previously introduced the ARMv8-R architecture, it’s time to look more closely into its new technology and explain some of the benefits it will bring.  I’ll try to convey the key concepts simply…

This year’s ARM TechCon conference in Santa Clara sees ARM disclosing details of its next processor architecture; ARMv8-R.  This eighth-generation ARM architecture is already established as …

This content was initially posted 16 July 2013 on blogs.arm.comIn the previous blog post we introduced VIXL - A Dynamic Code Generation Toolkit for ARMv8. This blog post will show you how to use the VIXL…

This content was initially posted 10 July 2013 on blogs.arm.comWe are pleased to announce the release of VIXL, a dynamic code generation toolkit for ARMv8 that we hope will enable JIT creators to rapidly…

How to get the most out of the memory interface  The choice of DDR memory is a key factor in determining the cost and power of the smartphone. Low cost smartphones typically use a single 32-bit memory…

ARM products in server and networking? Yes, it’s happening and AMBA® 5 CHI is a big part of making that happen. The AMBA 5 CHI protocol enables the latest ARMv8 architecture Cortex®-A50…

ARM® AMBA® 5 CHI Memory Controllers work in concert with AMBA 5 CHI interconnects to provide controls to optimise data flows between many processors and the DDR memory.  In this blog I am going to tell…

ARM Big.LITTLE processing addresses one of today's most significant challenges: extending consumers' always on, always connected mobile experience with both improved performance AND longer battery life…

Following on from two earlier articles (Navigating the Cortex Maze and ARMv6-M vs ARMv7-M - Unpacking the Microcontrollers), you might be interested in a new piece on the ARMv7-A architecture and Cortex…

Fact: The ARM architecture is the most widely licensed 32-bit embedded instruction set architecture in the industry. That fact makes the ARM Instruction Set Architecture (ISA) incredibly important to…

I thought I'd post a short blog post about commonly asked questions on AMBA 4 ACE and system coherency.What does ACE mean?ACE is the "AXI Coherency Extensions" introduced with the AMBA 4 specification…

The Arm Cortex-M story has much depth and warrants some further explanation. You see, it doesn’t end with Armv7-M.

This blog was originally posted on 11 September 2013 on blogs.arm.comFollowing on from the UEFI 64-bit announcement, I like to announce the release of the ARM® Architecture Reference Manual (commonly known…

Introduction The ARM architecture is 28 years old this year. The ARM1 first ran code on 26th April 1985 at the office of Acorn Computers in Cambridge, UK. Since the formation of ARM (then called “Advanced…

I saw what looks like the start of a series of short videos on the ARMflix YouTube channel. Of course, it doesn't go into much details, but I thought it was a simple way to discover the series. As they…

The implementation of multi-threading in multi-core processor systems is being heralded as a potential solution to the challenge of achieving ever-higher performance targets with strict limits on power…

In this blogpost, Gabor Ballabas and I share why and how we’ve set up a public buildbot for the LLVM AArch64 backend. This buildbot is part of the LLVM community’s continuous integration infrastructure…

This blog was originally posted on 22 February 2011 on blogs.arm.comARM processors have been predominant in the smartphone market and are becoming increasingly mainstream in the overall embedded space…

This blog was originally posted on 7th March 2011 on blogs.arm.comPreviously I introduced UEFI and its history, now I will get into its benefits, especially for the usage on ARM-based systems. I will further…

Note: This was originally published on the 14th of February 2012 at blogs.arm.com.I have recently been using the ARM Streamline profiler to study the behaviour of Mozilla Mobile Firefox (code-named Fennec…

This post is part of a series:Condition Codes 1: Condition Flags and CodesCondition Codes 2: Conditional ExecutionCondition Codes 3: Conditional Execution in Thumb-2Condition Codes 4: Floating-Point Comparison…