Architectures and Processors blog

It is possible to design and generate production ready optimized code for the Cortex-M4 without having to create a single line of code!Come to the 50 minute presentation on Wednesday, Oct 30th at 1pm at…

IntroductionARM recently announced the next in the family of CCN (Cache Coherent Network) solutions. Specifically we introduced the CoreLink CCN-508. A quick recap – CoreLink CCN-508 is a cache coherent…

To all those attending the ARM TechCon, come to the developer summit which is free and learn about practical hands on implementations secrets.  On Tuesday, October 29th at the Milpitas Meeting Room at…

Just over 6 years ago, in October 2007, ARM introduced a product that had the potential to change the world. Not just in one market (like mobile), but nearly all known semiconductor markets – Looking back…

IntroductionRecently I presented “Coherent Interconnect Technology Supports Exponential Data Flow Growth” at the Linley Processor conference in Santa Clara, CA where I announced a new ARM coherent interconnect…

IntroductionSmartphone and tablets are on the rise the increasing performance and convenience of these devices is definitely showing impact on the traditional PC market. Tablet sales will surge 53.4%,…

This document gives 10 tips on how best to use the FPU on the Arm Cortex-M4 processor.

A question that I am asked many times is – what is the fundamental difference between the high efficiency, mid range and the high performance application processors in the ARM Cortex family? The simple…

1 - Fast adoption The Cortex-M0+ processor was announced in March 2012, with two lead partners, namelyFreescale and NXP, who went public with their plans to release MCUs based on this new processor. These…

This is the third of three blogs I've written around the announcement of the new ARMv8-R architecture for real-time embedded processors.  Simon Craske, our Embedded Processor Architect, and myself will…

Abstract The complex task of selecting which processor core to license can be simplified by using a standard check list approach to evaluate all relevant criteria. This white paper goes through such a…

You might have come across some pieces I've written recently on the ARMv7 architecture.Navigating the Cortex MazeARMv7-A - Power to the PeopleARMv6-M vs ARMv7-M - Unpacking the MicrocontrollersI've…

In recent articles, I’ve overviewed the ARMv7 architecture and then looked in more detail at ARMv7-A (ARMv7-A - Power to the People) and ARMv6-M/ARMv7-M (ARMv6-M vs ARMv7-M - Unpacking the Micro…

This is the first in a series of blogs covering the migration towards ARM technology in the rapidly evolving telecom-infrastructure market. A lot has been written recently regarding the challenges facing…

Having previously introduced the ARMv8-R architecture, it’s time to look more closely into its new technology and explain some of the benefits it will bring.  I’ll try to convey the key concepts simply…

This year’s ARM TechCon conference in Santa Clara sees ARM disclosing details of its next processor architecture; ARMv8-R.  This eighth-generation ARM architecture is already established as …

This content was initially posted 16 July 2013 on blogs.arm.comIn the previous blog post we introduced VIXL - A Dynamic Code Generation Toolkit for ARMv8. This blog post will show you how to use the VIXL…

This content was initially posted 10 July 2013 on blogs.arm.comWe are pleased to announce the release of VIXL, a dynamic code generation toolkit for ARMv8 that we hope will enable JIT creators to rapidly…

How to get the most out of the memory interface  The choice of DDR memory is a key factor in determining the cost and power of the smartphone. Low cost smartphones typically use a single 32-bit memory…

ARM products in server and networking? Yes, it’s happening and AMBA® 5 CHI is a big part of making that happen. The AMBA 5 CHI protocol enables the latest ARMv8 architecture Cortex®-A50…

ARM® AMBA® 5 CHI Memory Controllers work in concert with AMBA 5 CHI interconnects to provide controls to optimise data flows between many processors and the DDR memory.  In this blog I am going to tell…