Not so many years ago, the term high-performance computing (HPC) was used primarily in the esoteric world of supercomputing and massively parallel processor arrays. Speed has always been important in electronics, but the demands placed by everyday consumer devices paled in comparison to the complex simulation workloads in high-end computing systems. This is no longer the case. On your phone, Siri, Google or Alexa, can answer queries or commands with lightning speed. Locally drawing upon a hyper-optimized computing-processor array, and leveraging millions to billions of petaflops of back-end processing. This is to make sense of your need for a slightly dimmed lamp or a different rice varietal with the Chicken Korma from the latest food delivery company of choice. And no longer is communication limited by locality; a computer, likely thousands of miles away, will seamlessly connect your phones' messaging app to the regular phone system of your favorite curry house, without even skipping a beat. "Did I say Basmati? I meant brown rice." Billions of compute cycles to assuage the whims of our evolving rice choices.Managing this voice and data traffic for a cellular network is a big challenge addressable only by extensive, compute-heavy infrastructure. Similarly, autonomous vehicles learn by sharing the experiences of many different vehicles in different driving situations. And, by massive processing-driven coalescence, understanding the many intricacies and vagaries of multitudes of driving styles and how to best traverse them. Beyond consumer devices, there are additional compute-intensive, cloud-based services, including social media platforms and cryptocurrencies. The complex algorithms to make all these applications work demand lots of computing powers. Since it is necessary to build the chips that do the computing, HPC drives the requirements for the silicon. This cannot be developed without extensive support from Electronic Design Automation (EDA) tools and the supporting IP solutions.
EDA technology is shaped in close collaboration with semiconductor providers. This is essential to achieve SoC power, performance, and area (PPA) targets at advanced process nodes while meeting rigid schedules that minimize time to market (TTM). Sophisticated EDA tools and high-quality, silicon-proven processor and interface IP are additionally part of the picture. As a leading EDA and IP vendor, Synopsys both leads and monitors industry trends and collaborates closely with key partners and customers to guide early and deliberate investments in the most important domains. This enables the company to innovate and bring to market new technologies that, in turn, help customers develop and release the new products of tomorrow. There is no better example of cooperation than the long-standing collaboration between Arm and Synopsys. This collaboration continues to enable mutual customers to realize innovative solutions, accelerating to market, secure, AI-enabled, and power-efficient HPC systems at the center of an increasingly insight-driven world. With Synopsys design and verification solutions and IP optimized for Arm® processor cores, chip developers can leverage the jointly developed flows and methodologies to meet the bandwidth and performance needed for their HPC applications.
Join Synopsys at Arm DevSummit to learn more about enabling compute in all its forms: Arm and Synopsys and the rise of democratized HPC.
Figure 1: Long history of collaboration between Arm and Synopsys on silicon to Software Solutions
Arm and Synopsys typically begin working on the core-specific reference flows very early during Arm-processor-core development. Thanks to the early start, Synopsys engineers can develop new tool capabilities and methodologies while the core is being created.
Once the core is released to early adopters and beyond, they receive a solution that includes recipes and methodologies to help achieve optimal PPA quickly. These optimized reference flows are available with QuickStart Implementation Kits (QIKs). QIKs are based on Synopsys Fusion Compiler, a unique RTL-to-GDSII digital implementation solution, whose single-data-model architecture enables a highly convergent system delivering better QoR and faster TTM. Consider these achievements from an Arm Neoverse N1 with 2.1 million instances at the 7nm process using Fusion Compiler RTL-to-GDSII solution:
Figure 2: Strong collaborations meeting customer demands
DesignWare® IP is created with capabilities specific to Arm Neoverse platform applications so that designers can tap into the full performance of their interfaces through the Arm subsystem. Together, these efforts help mitigate any performance bottlenecks and lower customer risks while making the final solution easier to use.
On the IP side, the collaboration includes Arm's CMN-700 coherent-mesh interconnect and Synopsys DesignWare Interface IP. IP blocks also play an essential role in supporting chiplet inter-die connectivity. PHY IP for SerDes-based 112G USR/XSR and parallel-based HBI interfaces supports the demand for efficient, reliable, power-efficient links with very low latency.
On the silicon side, the latest Arm Neoverse V1 and N2 platforms support the high workloads, performance demands, and power efficiency requirements for HPC, whether designing large SoCs or chiplets, an increasingly popular option. By combining multiple, single silicon dies onto one package, chiplets enable product modularity and optimized process node selection based on function. This provides another way to extend Moore's law while enabling product modularity and optimization of process node selection based on function. Arm provides customers with Neoverse reference design material, along with end-to-end testing to ensure interoperability and compliance at the system level.
Meeting PPA targets for chiplets and larger, faster, and more complex SoCs remains a race as designers strive to achieve increasingly stringent TTM goals. The Arm-Synopsys collaboration supports even the most demanding HPC requirements while reducing TTM and enabling successful end products. The long-standing, strategic collaboration between Arm and Synopsys ensures that designers using these platforms can meet PPA targets while shortening time to tapeout, often from weeks to days.
Catch up on these other recent HPC-related blog posts:
Register interest for Arm DevSummit 2022