The Arm DevSummit 2021 is coming up. It is an excellent reminder of the incredible pace of computing technology, from sensors to edge computing and hyperscale computing in data centers. And it is fascinating to watch the ever-accelerating cycle at which Electronic Design Automation (EDA) and computational software improve compute and, in turn, make EDA more productive, only to improve computing even further. Being part of this industry and partnering with Arm is like living in M.C Escher's lithograph "Relativity," only without the optical illusion. When arriving at the next staircase, we have elevated the industry to the next advanced level of computing.
Arm's Fellow and Director of Technology Rob Aitken's recent article "Performance per Watt Is the New Moore's Law" is an excellent reminder of our industry’s technology trends. Rob reviews some of the observations on technology direction that our industry lives by: Moore's law and Koomey's law. The IP and EDA industries have always used them to see where things are heading. We are now in an era that we at Cadence refer to as "More than Moore." Complexities that are close to or are exceeding the reticle limit and the demand for more domain specificity. Designs that become more optimized for specific workloads have pushed us beyond the boundaries of Moore's law and led to disaggregation of Systems on Chip (SoCs). 3D-IC is the answer, and we see much discussion on it at Arm DevSummit.
Back to "life in an Escher print." With the advances of massive parallelization in cloud computing, users evaluate the best configuration of computing infrastructures to execute HPC and EDA algorithms. At our virtual booth, you will find a presentation I gave with Tim Thornton and other colleagues at Arm on "Optimizing EDA Cloud Cycles." In it, I outlined some of the "high-cycle" consumers in the design flow that are especially suitable for parallelization, as illustrated in the following diagram.
When considering the throughput of execution versus pure wall-to-wall time and when accounting for power consumption and its cost impact, the results of using different compute architectures can be pretty impactful. Tim Thornton outlined some of their recent results on formal solvers in his recent blog post.
The bottom line—the latest computing configurations make EDA more productive. In turn, EDA is used to optimize the next-generation computing architectures, from sensors through edge computing to hyperscale computing. Several aspects are important here, including reliability and aging, safety, security, and architecture compliance.
Together with Arm, Cadence has been part of the ecosystem to drive towards improved security. Arm has laid out their vision in their "Security Manifesto." On security, I present together with Cadence’s strategic partner, Green Hills Software, on "Accelerating Safety and Security Verification of Arm v9-Based Systems to the Pre-Silicon Phase."
On reliability and aging, my colleague Paddy Mamtora will present together with Arm a session on how to "Gain PPA Advantage with New Aging-Aware STA Solutions for High-Performance Semiconductor Designs." For high reliability, applications such as automotive and defense must operate predictably over long periods. To ensure this high reliability, designers require accurate methods of analyzing future semiconductor performance without over-margining and impacting power, performance, and area objectives. Paddy will present a new aging methodology using an Arm high-performance library, featuring Cadence's Liberate and Tempus characterization and STA signoff tools.
In architecture compliance, Arm has introduced the "Server-Based System Architecture" (SBSA). Cadence's Nick Heaton will present with Arm in "Accelerating System-Level Verification of Arm CoreLink CMN-700-Based SoCs and Systems" on approaches to address and accelerate the complex system-level verification and performance analysis interconnects.
Finally, Cadence's Marc Greenberg illustrates the details of Arm’s AMBA 5 CHI interface protocol as it relates to the DRAM interface in "Moving to the AMBA 5 CHI Interface Protocol at the DRAM Interface."
All these examples at the Arm DevSummit will illustrate how we are improving the next generation of computing together with Arm and other ecosystem partners. In turn, this makes EDA and computational software more productive… And put us onto that next Escher staircase.
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