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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 729 Questions
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  • Answered

    Does AHB-Lite Protocol require the master processor to be pipelined? +1

    • AHB-Lite
    • Processor Architecture
    15431 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    APB process when pstrb = "0000" or "0101" during write transaction 0

    15051 views
    2 replies
    Latest over 6 years ago
    by Hyunkyu
  • Not Answered

    Dealing with Inout Ports - design and testbench writing 0

    • Verilog
    11989 views
    0 replies
    Started over 6 years ago
    by Kedhar Guhan
  • Answered

    How do I add AHB interface to a processor with Load Store Architecture? 0

    • Processor Architecture
    • AMBA 2 AHB Interface
    • AHB
    14792 views
    2 replies
    Latest over 6 years ago
    by Kedhar Guhan
  • Not Answered

    Axi4 Write Transaction 0

    • AMBA
    • AXI4
    13926 views
    1 reply
    Latest over 6 years ago
    by vstehle Arm Employee Badge
  • Not Answered

    State Machine for AHB-Lite Protocol 0

    • AHB-Lite
    • AHB
    16275 views
    3 replies
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst? +1

    • AXI
    16074 views
    2 replies
    Latest over 6 years ago
    by Zax
  • Not Answered

    Assertion for Multiple Transfer on APB Bus 0

    • APB
    • AMBA
    • Bus Architecture
    14663 views
    2 replies
    Latest over 6 years ago
    by Rakesh Venkatesan
  • Answered

    What purpose do wrapping BURST transfers serve? +2

    • AHB-Lite
    • AHB
    23428 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Can a simple processor with load-store architecture support BURST? 0

    • AHB-Lite
    • Processor Architecture
    • AHB
    13485 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Why does an AHB slave require HBURST signal? 0

    • AHB
    • Memory
    16657 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    What purpose does BURST feature in AHB serve? 0

    • Protocols
    • Architecture
    • AHB-Lite
    • Processors
    • AHB
    21944 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    Is there any scenario where HWDATA and HRDATA are used simultaneously? 0

    • AMBA 3 AHB Interface
    13551 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Bypassing all clock gates in Cortex-R52 (ARMv8) 0

    • Cortex-R52
    • FPGA
    12189 views
    0 replies
    Started over 6 years ago
    by Zack Yang
  • Not Answered

    [ARM GICv3 - GIC Stream protocol] An interrupt being retrieved from a CPU interface! 0

    • GICv3/v4
    • Generic Interrupt Controller
    13487 views
    1 reply
    Latest over 6 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    One question about the power pin connection on Arm Artisan 14nm 14LPP High-Speed Single-Port SRAM 0

    12468 views
    0 replies
    Started over 6 years ago
    by binbin
  • Suggested Answer

    When should APB slave Sample address/Data for read/write transaction from APB master? 0

    25565 views
    5 replies
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    AXI 4 UPsizer Downsizer module's protocol checker Error with WSTRB? 0

    13339 views
    2 replies
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Is during AXI unaligned transfer not all WDATA bits used? 0

    • AXI
    • AXI4
    14325 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    When Wrapping happens in AXI? 0

    • AXI
    • AXI4
    20938 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
<>
Topics being discussed in this forum
  • ACE
  • AEMv8 FVP
  • AHB
  • AHB5
  • AHB-Lite
  • AMBA
  • AMBA 5
  • AMBA 5 CHI
  • APB
  • Arm Development Studio
  • Armv8-M
  • AXI
  • AXI4
  • Bus Architecture
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  • CoreLink NIC-400 Network Interconnect
  • CoreSight
  • Cortex-A
  • Cortex-M
  • DesignStart
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  • Interface
  • socrates
  • TrustZone