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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 730 Questions
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  • Not Answered

    Interrupts and pipeline 0

    • Pipeline Control and Execution
    • Interrupt
    11788 views
    0 replies
    Started over 5 years ago
    by d.ry
  • Not Answered

    Normal store between exclusive transactions? 0

    • SoC Designer
    • Armv8-A
    • Semaphore
    12678 views
    1 reply
    Latest over 5 years ago
    by a.surati
  • Not Answered

    Welcome to the new Simulation Models forum 0

    1843 views
    0 replies
    Started over 5 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    TrustZone vs CMN 0

    11439 views
    0 replies
    Started over 5 years ago
    by Hunglin
  • Answered

    [NIC-400 Interconnect] Remap mode 0

    16156 views
    2 replies
    Latest over 5 years ago
    by Hieu Ho
  • Answered

    I am working on AXI vip and I am confused about where should I put logic about burst(FIXED,INCR,WRAP) can anybody give me direction ? +1

    • AXI4
    16328 views
    1 reply
    Latest over 5 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    Inconsistency in latest AXI4 specification (version g) regarding INCR burst transfers. +1

    • AXI4
    15249 views
    1 reply
    Latest over 5 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    AMBA 5 CHI Memory Attributes 0

    • AMBA 5 CHI
    14633 views
    1 reply
    Latest over 5 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    Compare the performance of In-order and Out-of-order in AXI protocol +1

    15939 views
    1 reply
    Latest over 5 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    CHI protocol cache line states +1

    • AMBA 5 CHI
    • SoC Verification
    18258 views
    1 reply
    Latest over 5 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior 0

    • AMBA
    • ACE
    • ACE 5
    • interconnect
    • AMBA 5
    30088 views
    7 replies
    Latest over 5 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    How do I use M1 designstart fpga on Nexys4 DDR? 0

    11328 views
    0 replies
    Started over 5 years ago
    by Roy Kravitz
  • Not Answered

    Question related to Phases in APB 0

    18079 views
    1 reply
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Is M3 DesignStart similar to M7 Design Kit? (I don't yet have M7 Design Kit) 0

    • Cortex-M7
    • Cortex-M3
    • DesignStart
    12556 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    How to process raw data from monitor and convert it into set of commands + data exchange? 0

    11536 views
    0 replies
    Started over 5 years ago
    by aditya raja
  • Not Answered

    ARM-A15 SoC integration for Simulation (VCS) How to Enable traces for debug 0

    12043 views
    0 replies
    Started over 5 years ago
    by Moti88
  • Answered

    I am working on protocol checker VC of APB4 to which I have to test the assertions written. Does it mean I have to write test cases to verify my assertions? 0

    14873 views
    1 reply
    Latest over 5 years ago
    by aditya raja
  • Not Answered

    Coresight Architecture: Is it possible to include AHB ROM tables as part of system ROM table? 0

    • CoreSight Architecture
    • CoreSight
    12709 views
    0 replies
    Started over 5 years ago
    by Vignesh J
  • Not Answered

    Executable name in DS-5 Linux project 0

    • DS-5 Development Studio
    • executable
    • compilation
    • Linux
    12291 views
    0 replies
    Started over 5 years ago
    by Yakov Erlich
  • Not Answered

    AXI4 master requirements for unaligned transactions (address v/s WSTRB) 0

    17683 views
    1 reply
    Latest over 5 years ago
    by guimers8
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Topics being discussed in this forum
  • ACE
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