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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 739 Questions
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  • Not Answered

    L4 cache in N1 SDP SoC 0

    8220 views
    2 replies
    Latest over 5 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    test cases for apb 0

    15387 views
    4 replies
    Latest over 5 years ago
    by Antonetta
  • Answered

    Number of masters/slaves in AHB 0

    11315 views
    1 reply
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Model debugger unstable when attempt to load more than one target +1

    3443 views
    3 replies
    Latest over 5 years ago
    by CDAMP
  • Not Answered

    L1 cache BW 0

    8226 views
    2 replies
    Latest over 5 years ago
    by Robert Wolff
  • Answered

    In AXI Why there is a read response in each data transfer? 0

    23044 views
    3 replies
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    C9912E: --cpu selected +1

    10768 views
    1 reply
    Latest over 5 years ago
    by Christiana
  • Not Answered

    AXI interconnect performance improvement 0

    9078 views
    1 reply
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    ICODE and DCODE Fetches 0

    • Cortex-M3
    8377 views
    0 replies
    Started over 5 years ago
    by eugch
  • Answered

    USB not detected 0

    4383 views
    4 replies
    Latest over 5 years ago
    by DRsecr
  • Not Answered

    what is different that change start address and use WSTRB signal for transfer 0

    8792 views
    1 reply
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    why use unaligned transfers in AXI 0

    11575 views
    1 reply
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    What purpose does SINGLE BURST feature in AHB serve? 0

    9633 views
    1 reply
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    What is peripheral and why use low-power in AXI 0

    8436 views
    1 reply
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    response ordering at AXI4 slave 0

    • AXI4
    11045 views
    4 replies
    Latest over 5 years ago
    by rvora
  • Not Answered

    about affinity routing in GICv3 (can't understand a figure in the document) 0

    • GICv3/v4
    8321 views
    1 reply
    Latest over 5 years ago
    by ckim
  • Answered

    Can AHB3_Lite master send an unaligend address? +1

    • AMBA 4
    • AXI4
    • AHB-Lite
    10715 views
    2 replies
    Latest over 5 years ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    AHB Split and Retry +1

    11135 views
    2 replies
    Latest over 5 years ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    AHB DeadLock: HREADY=0 & HTRANS=BUSY +1

    11519 views
    3 replies
    Latest over 5 years ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    AHB-lite Slave Burst Operation 0

    • AHB-Lite
    15833 views
    4 replies
    Latest over 5 years ago
    by eugch
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