Hi all,
I am working on a SOC using Xilinx ZYNQ US+ FPGAs. I am transferring data to DDR4 memory by AXI interconnect cores. I am going to find a way to improve the performance of my interconnect. I am wondering if there is something that I can do about this AXI interconnect core? First, I want to have AXI stream specification. How can I download it?
Thanks,
Hossein
I tried a quick web search for "axi stream" and after a few hits on Xilinx pages (which might help), further down the list of results was this link to the Stream spec on the ARM website, and there is a download button on that page...
developer.arm.com/.../About-the-AXI4-Stream-protocol