SoC Design and Simulation forum AXI interconnect performance improvement

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AXI interconnect performance improvement

Hi all,

I am working on a SOC using Xilinx ZYNQ US+ FPGAs. I am transferring data to DDR4 memory by AXI interconnect cores. I am going to find a way to improve the performance of my interconnect. I am wondering if there is something that I can do about this AXI interconnect core? First, I want to have AXI stream specification. How can I download it?

Thanks,

Hossein