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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 742 Questions
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  • Answered

    I have a question about the destination of HWRITE data signal. 0

    14029 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Basic Understanding for AXI WRITE INCR +1

    • AMBA 3 AXI Interface
    • AXI
    19792 views
    2 replies
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Embedded Trace Fifo(ETF) in Hardware FIFO mode flushing trace data 0

    • Embedded
    • SRAM Memory
    • Embedded Trace Macrocell
    • CoreSight
    • Debug and Trace
    • Memory
    17119 views
    2 replies
    Latest over 6 years ago
    by jeremy_ng
  • Answered

    How is the PREADY signal triggered low by the Slave in an APB? +1

    • APB
    • AMBA 3
    • Bus Architecture
    15485 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    what action will be performed by the master based on the read and write responce in axi 4? 0

    • AXI
    • AXI4
    16004 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    ACE protocol : Eviction and snoop request at same time +1

    • AMBA
    • L1
    • ACE
    • Cache
    16393 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Answered

    AXI3 write data interleaving with same AWID +1

    • AMBA
    • AXI
    19545 views
    4 replies
    Latest over 6 years ago
    by mveereshm622
  • Answered

    AHB revisions from AHB3 to AHB5 0

    • AMBA
    • AHB
    18821 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Burst termination with BUSY transfer on AHB 0

    • AMBA
    • AHB
    18355 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Regarding retry response +1

    • AMBA
    • AHB
    14126 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    APB3 Slave responding when PSEL = 0 +1

    • APB
    • AMBA
    17010 views
    2 replies
    Latest over 6 years ago
    by vshankar11
  • Answered

    What is expected from response if in WRAP txn in AHB is un-aligned. +1

    • AHB-Lite
    • AHB
    13784 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    AMBA +1

    • APB
    • AMBA
    • Bus Architecture
    13579 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Does AHB-Lite Protocol require the master processor to be pipelined? +1

    • AHB-Lite
    • Processor Architecture
    15651 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    APB process when pstrb = "0000" or "0101" during write transaction 0

    15384 views
    2 replies
    Latest over 6 years ago
    by Hyunkyu
  • Not Answered

    Dealing with Inout Ports - design and testbench writing 0

    • Verilog
    12021 views
    0 replies
    Started over 6 years ago
    by Kedhar Guhan
  • Answered

    How do I add AHB interface to a processor with Load Store Architecture? 0

    • Processor Architecture
    • AMBA 2 AHB Interface
    • AHB
    14971 views
    2 replies
    Latest over 6 years ago
    by Kedhar Guhan
  • Not Answered

    Axi4 Write Transaction 0

    • AMBA
    • AXI4
    14059 views
    1 reply
    Latest over 6 years ago
    by vstehle Arm Employee Badge
  • Not Answered

    State Machine for AHB-Lite Protocol 0

    • AHB-Lite
    • AHB
    16521 views
    3 replies
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst? +1

    • AXI
    16390 views
    2 replies
    Latest over 6 years ago
    by Zax
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