This is more of a conceptual doubt than a doubt in protocol. I've come across many papers where state machines are designed for AHB and AHB-Lite. I never understood why a state machine is required and where exactly is it incorporated(inside the processor or in the master interface?).
Also, during any point of time, there will be two transfers in two different states (address phase of current transfer coincides with data phase of previous transfer). So will there also be two different state machines deployed at any moment?
My IDLE-ADDRESS-DATA-IDLE example was really thinking of a VERY simple master design which only ever had one ongoing access. The AHB is pipelined, so the data phase of an access coincides with the address phase of the next access, but my simple master thinking was that the master would just be signalling IDLE transfers around NONSEQ accesses, so not having to consider SEQ accesses.
If you are looking at a master which could have 2 active (non-IDLE) transfers ongoing (one in the address phase, one in the data phase), you do really need to be building a state machine just tracking the address phase transfer sequences (mainly using HTRANS), and then register the address phase "state" using an HREADY=1 qualified HCLK rising edge to give you a data phase control (no need for a separate state machine).