Arm Community

Not Answered
How does QoS with priority and ordering allowed with AXI ID? 0
- AMBA
- AXI
- AXI4
14559 views

1 reply

Latest over 8 years ago
by Neil Parris
Suggested Answer
How does nic400 directs traffic from master to slaves? 0
- corelink interconnect
- CoreLink NIC-400 Network Interconnect
7735 views

3 replies

Latest over 8 years ago
by Martin Weidmann
Answered
AXI handshake between AW/AR-READY and B/R-RESP +1
- AMBA
- AXI
11765 views

2 replies

Latest over 8 years ago
by KalyanSuman
Answered
4k boundary in AXI +1
- AMBA
- AXI
- Interface
11770 views

2 replies

Latest over 8 years ago
by Martin Weidmann
Answered
axi read transfers +1
- AMBA
- AXI
- Interface
8672 views

2 replies

Latest over 8 years ago
by vidya
Answered
Could you give some tips on developing for ARMv8-M with IAR tools? +1
7320 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
What does Keil offer that GCC does not? +1
- Arm Compiler 6
- Arm Compiler
- Keil
- GCC
- TrustZone
- Armv8-M
12661 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
Does Cortex-M33 support TCMs? +1
7825 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
What is NSC? +1
- TrustZone
- Armv8-M
7521 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
Is the IDAU also run-time programmable? +1
- TrustZone
- Armv8-M
6795 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
With regard to slide 38 that talks about calling from secure code to non-secure code, can we assume that the registers pushed {r4-r11} cannot be viewed by examining the stack? +1
- TrustZone
- Armv8-M
6919 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
Will a BLXNS into a location which is marked as secure, end up in the non-secure state, or will there be an exception? +1
- TrustZone
- Armv8-M
7028 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
Is it possible to set a memory region from non-secure to secure at runtime? +1
- TrustZone
- Armv8-M
7203 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
Does a library exist for Python to use the secure features of ARMv8-M or can they only be accessed using ASM or C/C++? +1
- TrustZone
- Armv8-M
6981 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
At what point in time is the boot security map fixed into the chip? +1
- TrustZone
- Armv8-M
6595 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
What sort of visibility does a non-secure debugger have of the secure sections? +1
- TrustZone
- Armv8-M
6485 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
Can secure accesses access both secure and nonsecure address map, whereas, nonsecure only access nonsecure part of the address map. +1
- Armv8-M
6219 views

1 reply

Latest over 8 years ago
by Ed Player
Answered
How did you measure the Instruction cache efficiency? Just code execution from Flash? Reading data from Flash? Programming data to Flash? +1
7082 views

1 reply

Latest over 8 years ago
by Mike EFTIMAKIS
Answered
Can you explain why you propose having two cores in your CoreLink SSE-200? +1
7869 views

1 reply

Latest over 8 years ago
by Mike EFTIMAKIS
Answered
Is the Corelink SSE-200 Subsystem available for Cortex M23? +1
- Corelink
- Cortex-M23
- Cortex-M3
- Cortex-M
- CoreLink SSE-200
- Cortex-M33
- Armv8-M
6386 views

1 reply

Latest over 8 years ago
by Mike EFTIMAKIS

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How does QoS with priority and ordering allowed with AXI ID? 0

How does nic400 directs traffic from master to slaves? 0

AXI handshake between AW/AR-READY and B/R-RESP +1

4k boundary in AXI +1

axi read transfers +1

Could you give some tips on developing for ARMv8-M with IAR tools? +1

What does Keil offer that GCC does not? +1

Does Cortex-M33 support TCMs? +1

What is NSC? +1

Is the IDAU also run-time programmable? +1

With regard to slide 38 that talks about calling from secure code to non-secure code, can we assume that the registers pushed {r4-r11} cannot be viewed by examining the stack? +1

Will a BLXNS into a location which is marked as secure, end up in the non-secure state, or will there be an exception? +1

Is it possible to set a memory region from non-secure to secure at runtime? +1

Does a library exist for Python to use the secure features of ARMv8-M or can they only be accessed using ASM or C/C++? +1

At what point in time is the boot security map fixed into the chip? +1

What sort of visibility does a non-secure debugger have of the secure sections? +1

Can secure accesses access both secure and nonsecure address map, whereas, nonsecure only access nonsecure part of the address map. +1

How did you measure the Instruction cache efficiency? Just code execution from Flash? Reading data from Flash? Programming data to Flash? +1

Can you explain why you propose having two cores in your CoreLink SSE-200? +1

Is the Corelink SSE-200 Subsystem available for Cortex M23? +1