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AXI handshake between AW/AR-READY and B/R-RESP

KalyanSuman

In AXI Write how the handshake between AW channel and B channel is taken care.

Standard says that 

"the slave must wait for both WVALID and WREADY to be asserted before asserting BVALID"

Does that means BVALID will never be asserted in the same cycle of AWREADY or WREADY? 

 

Similarly on the read channel standard says 

"the slave must wait for both ARVALID and ARREADY to be asserted before it
starts to return read data by asserting RVALID."

Does that means RVALID will never be asserted in the same cycle of ARREADY? 

 

KalyanSuman KV

  • +1
    No to both your questions.

    What the spec is saying is that for writes the final write data transfer must have completed (so WVALID, WREADY and WLAST all sampled high on an ACLK rising edge) before the slave can return a BVALID response.

    When the slave does signal BVALID, the slave could also be driving AWREADY and WREADY high to indicate it could accept new address and data transfers.

    Similarly for read transfers the spec is saying that the slave cannot drive RVALID high until the read address transfer has completed (so ARVALID and ARREADY both high on an ACLK rising edge).

    There is nothing to stop the slave driving ARREADY high to signal it can accept another address at the same time as returning read data (RVALID asserted) for an earlier accepted read address transfer.