Hello everyone!Hope ure all doing well.I've got several questions regarding the AMBA AHB specification "IHI0033C_amba_ahb_protocol_spec"1.) When is HRDATA actually valid for sampling & when is it actually driven??SCENARIO A) DRIVEN BY THE SUBORDINATE AT: the negedge of the clock inside the clock cycle of the data_phase &SAMPLED BY THE MANAGER AT: the positive edge of the clock cycle that follows right after the data_phase has finished?SCENARIO B)DRIVEN BY THE SUBORDINATE AT: the positive edge of the clock cycle after data_phase &SAMPLED BY THE MANAGER AT: combinationally or at the negedge of the clock that follows?2.) Does the same apply to HRESP and HREADY?3.) What does the specification mean by AMBA AHB being a single edge protocol? Using only the positive edge or the negative edge? but does that mean the subordinates as well or the sampling of the manager or the entirety of the SoC?4.) If HRESP, HREADY & HRDATA are sampled AFTER the data_phase is finished (2 clock cycles after the the transaction has been sent by the manager or sampled by the subordinate, 1 for the control_phase + 1 for the data_phase), How does the manager get to know that there was an error with the transaction it sent 2 CLOCK CYCLES ago? (since there are already at least 1 or more transactions sent by the Manager during that time)5) If the subordinate requires more time to finish an operation, and asks for wait states, how does that happen exactly in the case of pipelining, since again as stated above, the subordinates responses are sampled at least 1.5 or 2 clock cycles later after it was initially sent.
Let's use one of the diagrams from the AHB specification as an example when looking at your ABCD steps, so from ARM IHI 0033C have a look at figure 3-5 as it has Tx reference labels on each HCLK rising edge.
So if we are looking at transfer A in figure 3-5, T0 is probably what you referred to as A, the start of the transfer address phase, manager sending this request to the subordinate.
T1 is when the subordinate samples the address phase request, so the subordinate now knows what transfer is being requested by the manager, so point B in your list, and the transfer data phase starts, which is C in your list.
And at T2 this is the end of the data phase of the transfer, the subordinate samples the data being written, or the manager samples the read data the subordinate is returning, and would be D in your list.
I think what you are describing as the "control phase" is what the AHB protocol refers to as the transfer "address phase", which is when the manager is passing the address and control information to the selected subordinate. There is no "control phase" in addition to the "address phase".
If the subordinate needs additional time to perform the requested data transfer it can add wait states using HREADY, and these extend the data phase operation. This is what you see in figure 3-5 for transfer B, where the data phase extends from T2 to T4 because HREADY was sampled low at T3.
Please have a read at the AHB protocol as this shows how transfers are performed, and how the address and data phases of the transfers are pipelined to maximise bandwidth. If you then have questions, please try and refer to diagrams in the protocol document so we have a common reference for discussions.