HI, I have puzzle
if I am write something like that
initial begin$dumpfile("dump.vcd");$dumpvars(1);#100ns rst_n = 0;#100ns rst_n = 1;
// Align to negedge to drive traffic#5ns;
awaddr = 'h15;awvalid = 1;#10nsawaddr = 'h25;wvalid = 1;wdata = 'h10;
#10nsawaddr = 'h35;wdata = 'h20;
#10nsawvalid = 0;wdata = 'h30;
#10nswvalid = 0;#100ns$finish();
What should be come out for first Address 0x15 or 0x25 for slave according to axi4 protocol.BR,
Mayank
Hi Colin,
I asked for 2ns and 4ns because1- when I kept 10ns clk period means #5ns clk=~clk, for my RTL all three addresses were captured (0x15,0x25,0x35)and seen in Simulation for test scenario of initial post of this thread.2- But when #1 ns clk=~clk or #2ns clk=~clk , my middle address i.e 0x25 was not captured and not seen in simulation so what can be role of clk if any role?this is last question .Thanks & Regard.
There isn't any AXI protocol reason for the failure you are seeing, so it sounds as if some RTL code in your design has delays built into it such that it can't operate with the faster clocks. Do any of your modules have # delays in them ?
Sir
My RTL have only flopped delay
now your reply seems that my RTL has limitation with clk because at 10ns it was working fine with above scenario but with 4ns middle address does not seem. so AXI clk frequency limitation exists .Does it make sense?BR,Mayank
What is it that you are simulating ?
If this is a netlist, it will obviously have cell delays that will add up on combinatorial paths to limit the maximum frequency the design can be clocked at (nothing specific to AXI there).
If this is behavioural verilog it would run with simulation delta delays (unless there were # delays in the code), so there wouldn't be any limitation on the clock frequency.
Looking at this purely from an AXI protocol perspective there is no maximum ACLK frequency, so the only limitation are implementation specific limitations imposed by the design complexity and the cell library you are synthesising the design on.
You mention "flopped delay", so is this a synthesis cell library delay, or is it a behavioural simulation # delay ?
There isn't really anything anyone else can help with here, the delays limiting clock frequency are in your design RTL code.
Sir I am using functional simulation delay of one FF delay.I am not going to use cell, microcell, floorplanning, place and route etc.thanks
Then it is this "functional simulation delay of one FF" that is somehow limiting the frequency you can run your system.
You will need to look at how long this delay actually is, and why that is stopping the design being able to sample inputs and generate outputs within the ACLK cycle timings.