HI, I have puzzle
if I am write something like that
initial begin$dumpfile("dump.vcd");$dumpvars(1);#100ns rst_n = 0;#100ns rst_n = 1;
// Align to negedge to drive traffic#5ns;
awaddr = 'h15;awvalid = 1;#10nsawaddr = 'h25;wvalid = 1;wdata = 'h10;
#10nsawaddr = 'h35;wdata = 'h20;
#10nsawvalid = 0;wdata = 'h30;
#10nswvalid = 0;#100ns$finish();
What should be come out for first Address 0x15 or 0x25 for slave according to axi4 protocol.BR,
Mayank
Then it is this "functional simulation delay of one FF" that is somehow limiting the frequency you can run your system.
You will need to look at how long this delay actually is, and why that is stopping the design being able to sample inputs and generate outputs within the ACLK cycle timings.