HI, I have puzzle
if I am write something like that
initial begin$dumpfile("dump.vcd");$dumpvars(1);#100ns rst_n = 0;#100ns rst_n = 1;
// Align to negedge to drive traffic#5ns;
awaddr = 'h15;awvalid = 1;#10nsawaddr = 'h25;wvalid = 1;wdata = 'h10;
#10nsawaddr = 'h35;wdata = 'h20;
#10nsawvalid = 0;wdata = 'h30;
#10nswvalid = 0;#100ns$finish();
What should be come out for first Address 0x15 or 0x25 for slave according to axi4 protocol.BR,
Mayank
I'm not sure what you mean when you describe the 2ns and 4ns values, but if this is like the second question, asking about the clock frequencies the AXI protocol can run at, the same applies for any bus specification and it is not the protocol that limits the maximum frequency, but instead is a combination of the system design complexity, the silicon process being targeted, and also the tightness of the synthesis constraints being applied to the design.
The AXI protocol only uses rising edges of the ACLK signal for events, so all AXI paths have a full ACLK cycle for signal propagation, with outputs driven on one ACLK rising edge and inputs sampled on the next ACLK rising edge. So it is the complexity of that single cycle path that will decide how fast you can clock it, with larger designs usually meaning longer combinatorial paths between registers.
The silicon process and synthesis constraints applied are outwith the realms of the AXI spec, so I won't try and describe them here.