Question about amba ahb5 wait states

Hello. I have a question about ahb5's wait states. 

In ahb protocol specification 3.7.1 and 3.7.2, the change of HTRANS and Address, Why does Master inserts IDLE and busy transfer? Is this because the Maser has to change transfer type and address? 

If the master doesn't have to change the type or address, It is right to just maintain the the control signal, address, data?