I'm having trouble with interpreting the AHB specification regarding what should happen when two pipelined non-burst transactions are both expected to fail (in my test I am generating transactions such that they both should be seen as invalid by the slave).
In Figure 5.1 of the specification, I understand that a correct error response to transaction A is given between T2 and T4, and that transaction B is cancelled.
However, I am not sure that what is the reason why transaction B is cancelled:
Is it cancelled due to HTRANS == IDLE in T3-T4, or is it cancelled implicitly due to the error response to transaction A?
Should the master always issue HTRANS = IDLE when an error occurs, and a second transaction (B in this case) that is known by the master to be in its address phase while an error in the transaction that immediately precedes it is signaled?
Should the master expect transaction B to always fail when transaction A fails?
Suppose that in T3-T4, HTRANS was not equal to IDLE, and I expect that transaction B should be rejected by the slave, should I expect a second error response, in the same manner as in transaction A (T1~T3)?