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Hi, I am jang-hyun Son, a college student from South Korea.
I will study Mali GPU with OpenCL, and before that, I am now studying about the Mali G71 architecture.
My question is that, Why are there multiple(actually 4) L2 Caches in the image above.
I think only one L2 cache is used for one GPU normally.
Thank you for reading my question, and i wish you a reply.
Thank you very much.
Then, one more question comes to my mind. I found AMBA 4 ACE is used for cache coherency.
Because of the multiple L2 caches, is it required to put AMBA 4 ACE under each of L2Cs for L2 cache coherency?
I am sorry for multiple questions, and thank you again.
The external memory interface can be coherent using ACE (silicon partner implementation choice - it's optional). All cache slices behave a single logical cache, so must correctly handle ACE irrespective of the number of slices.
HTH, Pete