Control signals during burst termination with BUSY transfer on AHB

I saw that,

1. Under these circumstances, it is acceptable for the Manager to then perform a NONSEQ or IDLE transfer that then effectively terminates the undefined length burst

2. When a master uses the BUSY transfer type the address and control signals must reflect the next transfer in the burst.

But I'm confused about this case:

TIME: T1 T2 T3 T4
HTRANS:    NSEQ    SEQ    BUSY    NSEQ
HADDR: 0x02 0x03 0x04 0x04
HWDATA: dataA dataB dataC dataC
HREADY: 1 1 1 1
HBURST: INCR INCR INCR4 INCR4

HBURST is changed to INCR4 at T3, is this legal?