Does the Cortex M0+  Single-Cycle IO Bus have an address bus to decode multiple IO sets for read and write?

I have an interest in the M0+ single-cycle IO Bus interface.

It seems that while the TRM describes a 32-bit bus, and a memory map it isn't clear if there is also an address bus to go along with this.

When instantiating do we have an IO address bus, and IO read/write signal as well? If so, how larger is the provided address bus for decode?

Thanks!

-Alan