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  • Not Answered

    AHB starting address? 0

    • AHB
    6888 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Is there a limit on the number of APB slaves on the AHB to APB bridge? 0

    • AMBA
    • AHB
    8764 views
    2 replies
    Latest over 7 years ago
    by Logicallyfit
  • Suggested Answer

    Interrupt status in Aarch64 0

    • Cortex-A9
    • AArch64
    • Cortex-A
    5920 views
    1 reply
    Latest over 7 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    Three question on AXI transfers, related to disjoint byte access in a single 4 byte word, single transfer. 0

    • AXI
    12695 views
    2 replies
    Latest over 7 years ago
    by DHDHD
  • Suggested Answer

    Why H/W watchdog is disabled in startup code?? 0

    7263 views
    1 reply
    Latest over 7 years ago
    by uditknit
  • Answered

    Booting sama5d2 with lpddr2 0

    • Cortex-A5
    • Cortex-A
    7936 views
    2 replies
    Latest over 7 years ago
    by Fredrik
  • Not Answered

    single burst in ahb lite 0

    • AHB-Lite
    • AHB
    8820 views
    2 replies
    Latest over 7 years ago
    by rajaraman r
  • Not Answered

    HREADY signal and single transfer in ahb lite 0

    • AHB-Lite
    9720 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    How interrupts are routed in EL3/EL2/EL1 mode 0

    • EL1
    • Generic Interrupt Controllers
    • EL3
    • EL2
    • ARMv8 Exception Model
    • Arm64
    • Interrupt
    9682 views
    1 reply
    Latest over 8 years ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    TRace 0

    • ETM
    • Trace
    • system trace macrocell
    6163 views
    1 reply
    Latest over 8 years ago
    by Guilherme Marshall Arm Employee Badge
  • Answered

    ARM CoreLink MMU-500 System Memory Management Unit - Preloading the TLBs and page tables +1

    • CoreLink MMU-500
    • Memory Management Unit (MMU)
    6327 views
    1 reply
    Latest over 8 years ago
    by Peter Rielly Arm Employee Badge
  • Answered

    Can I use LAPACK with Cortex-M4? 0

    • Cortex-M
    • Cortex-M4
    12557 views
    2 replies
    Latest over 8 years ago
    by Michelle Tseng
  • Not Answered

    AHB WRAP4 transfer 0

    • AHB
    6288 views
    2 replies
    Latest over 8 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    GICR_WAKER.ChildrenAsleep conditions to go to 0x0, post PE power-up 0

    • GICv3/v4
    • System Controllers
    • Generic Interrupt Controller
    7196 views
    3 replies
    Latest over 8 years ago
    by Danish
  • Answered

    ARMv8-64 Cache management in a PSCI functions 0

    • Power State Coordination Interface (PSCI)
    • Cache
    8897 views
    4 replies
    Latest over 8 years ago
    by Jorge
  • Suggested Answer

    Combining function attributes in C 0

    • C
    7000 views
    2 replies
    Latest over 8 years ago
    by vinkot Arm Employee Badge
  • Answered

    Embedded ARMv8 dev board 0

    • Cortex-A57
    • Armv8-A
    • Cortex-A75
    • Cortex-A
    7176 views
    1 reply
    Latest over 8 years ago
    by cdhmanning
  • Suggested Answer

    WLAST blocked when AXI Master timeout with VIP slave 0

    • AXI
    9534 views
    1 reply
    Latest over 8 years ago
    by Colin Campbell Arm Employee Badge
  • Discussion

    Cortex R

    • Cortex-R52
    • Cortex-R
    • cortex-r8
    • Cortex-R7
    5900 views
    1 reply
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    Regarding ARMv8M processor Cortex-M23 0

    • Cortex-M23
    • Cortex-M
    • Armv8-M
    6954 views
    2 replies
    Latest over 8 years ago
    by Joseph Yiu Arm Employee Badge
<>
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