HREADY signal and single transfer in ahb lite

HI...

A)

     1). I am now using a continuously 10 transfer of the SINGLE BURST write based read transfer. In spec says the default ready signal is HIGH.

     2).First thing i complete the first transfer of the write based read operation.

    3). Then it takes the busreq for one clock,grant for one clock and one extra clock.After the second transfer is started.

    4). In between the first and second transfer the HREADY will be should be low or HREADY should be high.

............................

B) This is another

 I am using the AHB lite. 

  clk1                clk2                           clk3            clk4             

  trans=2           trans=2                    trans=2
   
   add(A)            add(A)      
                       write-data(A)

                                                   read_data(A)


This is the lite spec. so the single master single slave.

  1)This is  single transfer so trans=2. First the i am write the write_data(A),At the time the time trans also maintained in clk2.

   2)/Again i am read the same address the value read_data(A), This is also trans maintained in clk3.

This correct or not.