• State Accepted Answer
  • +1 person also asked this people also asked this
  • Replies 5 replies
  • Subscribers 141 subscribers
  • Views 12235 views
  • Users 0 members are here
Options
Related
How was your experience today?

ARMv8 Exception level on Startup

Ajeesh

Hi,

When i power on a ARM cortex A57, How many of the 4 Exception levels will be supported?

How can i set such that only exception levels EL0 and EL1 are supported in my program? How can i activate each exception levels?

I have to set it such that normally the app should work on EL0 and when an exception occurs, it should go to EL1. How can i do that?

 

regards,

Ajeesh

  • +1 Arm Employee Badge
    The Cortex-A57 supports all four Exceptions levels (EL0/1/2/3), and at reset you will be in EL3. The initial Execution state (AArch32/AArch64) is controlled by a reset signal.

    To "not support" EL2/3 in your software:

    Your boot code would need to route the asynchronous exceptions (IRQ/FIQ/SError) to EL1, using SCR_EL3 and HCR_EL2. If you wanted to prevent re-entry to EL2/3, you'd also need to disable use of the SMC and HVC instructions. This is also controlled via SCR_EL3 and HCR_EL2.

    You'd also have do a bunch of standard initialization before entering EL1 for the first time. For example, initializing SCTLR_EL1 to a known/safe value and setting a known VMID (assuming Non-secure state).

    Once you'd done the initialization, execute ERET to drop to EL1. You'll need to have set up ESR_ELx/ELR_ELx and the RW bits before this.

    If you have access to DS-5, it includes a number of examples that drop from EL3 to EL1 after boot. They'd be a good starting point to see what's necessary.

    Can I ask why you want to take this approach?

    It's typical to have different software running at different ELs. For example, SoC/board specific firmware at EL3 and an OS at EL1. The EL1 software doesn't "support" EL3 exactly, but EL3 is being used in the system.
  • 0 in reply to Martin Weidmann
    Hi,
    Thanks for the reply.
    So if the board start up in EL3, when the IRQ ocuurs, Is it safe to assume that executed handler will be the handler from the vector table for EL3 only?
    How do i take an exception to the higher level(EL0 - EL1 etc..)?
    i meant, How do i chose a particular interrupt should occur in a particular exception level?

    >> Can I ask why you want to take this approach?
    -- I have some code (including startup) written for arm cortex-A9(a bare-minimum OS with a simple scheduler). I would like to port the code without any change to Aarch64. Only IRQ was enabled in the previous case. No FIQ, no SWI, no MMU, just a start up and a scheduler that schedule the tasks i create on priority base.
    I am not quite getting this 4 exception states. Wouldn't it be easier to do the above in a single exception state?

    regards,
    Ajeesh
  • 0 in reply to Ajeesh

    AFAIK, interrupts/exceptions in EL0/EL1 go to the vector table which belongs to the current state.

    You can define, if exceptions in EL1 go up to EL2/EL3.


    But I would not recommend to stay in EL2/EL3 but rather switch to EL1 which is similar to the SYS/SVC mode on ARMv7-A.