Does anyone know if there is a list of ARM instruction set pseudo instructions?
Or better yet, an instruction list like PPC's, where there is a list of 'true instructions' with mnemonics and
another list of "simplified mnemonics" (=pseudo instructions) in terms of the "true instructions" (mnemonics).
There are 499 ARM instructions listed in ARMv7-A/R ARM and going through them one by one is quite a job.
The "true" PPC instructions are explained much like ARM instructions in ARMv7-A/R ARM, but in the
"simplified mnemonics" chapter the pseudo instructions are described like:
How many pseudo instructions (roughly) are there for Cortex-A7?
ARMv7-A/R ARM doesn't seem to make a difference.
The basic LDR/STR instructions (bits 27 - 25 = 0 1 0 or 0 1 1) are pseudo instructions and there is really
two basic "single data load/store" instructions: the immediate form and the register form.
The special LDR/STR instructions (bits 27 - 25 = 0 0 0) (LDRH, STRD, ...) are different instructions:
the instruction bits have different meanings and/or are in different places.
Also some PC-related instructions are "true", because unlike with other registers, using PC also loads
the CPSR, so it's functionally different even if the encoding bits are exactly the same.
In addition to those:
LSL{S}<c> <Rd>, <Rm>, #0 ==> MOV{S}<c> <Rd>, <Rm>
LDM/LDMIA/LDMFD/LDMDB/LDMEA/LDMIB/LDMED and the STM-equivalents are all pseudo
instructions on top of anonymous instruction similarly to the basic LDR/STR instructions.
I consider them pseudo instructions, because the different mnemonics only define certain values
for the instruction modifier bits.
c c c c 1 0 0 B I M W L n n n n r r r r r r r r r r r r r r r r ?M<c> <Rn>{!}, <registers>
where B= before/after (1=before), I = increment/decrement (1=increment)
M= current mode/user mode (0=current), W=writeback, L=load/store(1=load)
So LDMIA<c> <Rn>! <registers> ==> "?M" where L=1, I=1, B=0, M=0 and W=1.
All (or at least nearly all) the other instruction encoding overlaps are actually "true" instructions, not pseudos.
Like ROR{S}<c> <Rd>, <Rm>, #0 --> RRX{S}<c> <Rd> (almost but not quite similar - 1 shift, sign extend)
and MSR{<c>}{<q>} <spec_reg>, #<imm> that becomes a hint (defined by the imm) if spec_reg bits are all zeros.
Yes, I think, you're right. There are not very many pseudos, but "true" overlapping instructions.
(Same encoding, but specific operand value, and the instruction changes into another instruction.)
Darn, the instruction set is (made?) complicated.