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cache misses
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cache misses
zhangyumao
over 6 years ago
Support for three outstanding data cache misses?
请问这句话是什么意思呢?
Top replies
william gao
over 6 years ago
+4
verified
这是cache硬件设计细节的参数,能减少pipeline停顿,增加L1 cache回填的带宽。 当L1 cache miss之后,cache控制逻辑会访问下级memory进行回填,这往往非常耗时,并且cache会block住后续的pipeline对cache的访问,从而使得memory访问延迟直接对pipeline可见。CPU支持3个outstanding cache miss,表示CPU可以在cache...