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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Not Answered

    Global variable initialisation problem 0

    • Cortex-M3
    1794 views
    0 replies
    Started over 5 years ago
    by Maitland
  • Not Answered

    Cortex-M3 Registers 0

    2775 views
    4 replies
    Latest over 5 years ago
    by Andy Neil
  • Not Answered

    Speculative data fetching on ARMv7-M 0

    • Armv7-M
    • Cache
    4655 views
    2 replies
    Latest over 5 years ago
    by MikeRobo
  • Not Answered

    Cortex-M3 Registers 0

    6569 views
    10 replies
    Latest over 5 years ago
    by Fabiano Junqueira
  • Answered

    FPB BreakPoint(without Debugger) 0

    • Armv7-M
    • Debugging
    • Cortex-M4
    4811 views
    3 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    Make MPU be uniprocessor system 0

    17050 views
    3 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    Trouble configuring MMU for 2MB block mapping 0

    • Memory Management Unit (MMU)
    18133 views
    1 reply
    Latest over 5 years ago
    by jcal93
  • Not Answered

    How to write to DHCSR register in Cortex-M 0

    • CoreSight Debug and Trace
    • 12 (Debug Monitor)
    • Cortex-M
    4593 views
    2 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    System wide cache flush 0

    • Cortex-A35
    • Cache coherency
    • Armv8-A
    • Cache Management
    21287 views
    5 replies
    Latest over 5 years ago
    by Norbert Goldstein
  • Not Answered

    Exec latency for ASIMD instructions taking the V pipelines 0

    18021 views
    2 replies
    Latest over 5 years ago
    by sjub
  • Answered

    Cortex A53 Bare metal booting have FIQ exception. How to debug? 0

    • Cortex-A53
    • CoreSight Architecture
    • Baremetal
    19222 views
    1 reply
    Latest over 5 years ago
    by Ben Chen
  • Suggested Answer

    Can not configure RCC by using HSE as system clock source 0

    3668 views
    1 reply
    Latest over 5 years ago
    by Andy Neil
  • Answered

    run standalone software in user mode 0

    18769 views
    5 replies
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    -print-libgcc-file-name gives thumb while -marm is used 0

    • GCC
    • Thumb
    • GNU Arm
    • Cortex-A7
    17355 views
    2 replies
    Latest over 5 years ago
    by Arjan
  • Not Answered

    data cached during level-2 page walk 0

    16684 views
    2 replies
    Latest over 5 years ago
    by XNoOp
  • Answered

    Can I change the frequency of the generic timer in armv8? 0

    18666 views
    2 replies
    Latest over 5 years ago
    by zilly
  • Not Answered

    Jitter in a square wave generated by using GPIO. 0

    15769 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    io coherency and shareability +1

    • Cache coherency
    • Cache Coherent Interconnect
    • coherency
    21178 views
    1 reply
    Latest over 5 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Programming the LPC1857 flash memory using the DAPLink project 0

    1892 views
    0 replies
    Started over 5 years ago
    by Fabiano Junqueira
  • Answered

    How to do the ARM state change between 64-bit and 32-bit? 0

    • 32-bit
    • AArch64
    • Armv8-A
    • 64-bit
    • AArch32
    94878 views
    10 replies
    Latest over 5 years ago
    by Su40mmer
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