Hi!
I am using an ARM Cortex-M23 microcontroller. I wish to pad every subroutine with certain number of bytes. Using the ALIGNALL attribute on an execution region I am able to achieve some success but I cannot control the number of bytes. Further, the ALIGNALL attribute does not seem to work on veneer code. While I can place the veneer code in a separate execution region, I cannot align the veneer code as I please. Is there any way to achieve what I am trying to do?
Thank you
Can you post your scatter file. It may help to help you.
Ah, and maybe tell which tool chain you are talking about.
Hello
The contents of my simple scatter file are provided here:
LR_ROM 0x10040000 0x10000 { ER_ROM_CODE +0 ALIGNALL 32{ *.o (+RO) } } LR_ROM2 0x10050000 { ER_ROM_CODE2 +0 ALIGNALL 32{ *(Veneer$$Code) } ; ER_ROM_UNUSED +0 FILL 0xFFFFFFFF (0x40000 - ImageLength(ER_ROM_CODE)) { ; } RW_IRAM_THREAD_CODE 0x30008000 0xE800 { *(+RW, +ZI) } }
I am using the MDK-ARM toolchain. The toolchain version is 5.30.0.0. Please let me know if you need any other information. Thank you
Guessing: DS 5: ALIGNALL works fine for me.
Do you mean the DS-5 toolchain?
So you are telling, section ER_ROM_CODE2 does not align?I tried a simple example, but hat no veneers inside, so I could not test this, but using some other custom section names alignment did work correctly.DS5 = DS-5, yes. But the compiler/linker is the same as in Keil.
Yes. ER_ROM_CODE2 does not align. For example, this is an excerpt from the NonSecure.txt file generated by the linker.
** Section #2 'ER_ROM_CODE2' (SHT_PROGBITS) [SHF_ALLOC + SHF_EXECINSTR + SHF_ARM_PURECODE] Size : 120 bytes (alignment 32) Address: 0x10050000 $t $Ven$TT$L$$SecureContext_SaveContext 0x10050000: b403 .. PUSH {r0,r1} 0x10050002: 2000 . MOVS r0,#0 0x10050004: 0200 .. LSLS r0,r0,#8 0x10050006: 3000 .0 ADDS r0,#0 0x10050008: 0200 .. LSLS r0,r0,#8 0x1005000a: 300c .0 ADDS r0,r0,#0xc 0x1005000c: 0200 .. LSLS r0,r0,#8 0x1005000e: 30a9 .0 ADDS r0,r0,#0xa9 0x10050010: 9001 .. STR r0,[sp,#4] 0x10050012: bd01 .. POP {r0,pc} $Ven$TT$L$$SecureContext_LoadContext 0x10050014: b403 .. PUSH {r0,r1} 0x10050016: 2000 . MOVS r0,#0 0x10050018: 0200 .. LSLS r0,r0,#8 0x1005001a: 3000 .0 ADDS r0,#0 0x1005001c: 0200 .. LSLS r0,r0,#8 0x1005001e: 300c .0 ADDS r0,r0,#0xc 0x10050020: 0200 .. LSLS r0,r0,#8 0x10050022: 30a1 .0 ADDS r0,r0,#0xa1 0x10050024: 9001 .. STR r0,[sp,#4] 0x10050026: bd01 .. POP {r0,pc} $Ven$TT$L$$SecureContext_AllocateContext 0x10050028: b403 .. PUSH {r0,r1} 0x1005002a: 2000 . MOVS r0,#0 0x1005002c: 0200 .. LSLS r0,r0,#8 0x1005002e: 3000 .0 ADDS r0,#0 0x10050030: 0200 .. LSLS r0,r0,#8 0x10050032: 300c .0 ADDS r0,r0,#0xc 0x10050034: 0200 .. LSLS r0,r0,#8 0x10050036: 3089 .0 ADDS r0,r0,#0x89 0x10050038: 9001 .. STR r0,[sp,#4] 0x1005003a: bd01 .. POP {r0,pc} $Ven$TT$L$$SecureContext_FreeContext 0x1005003c: b403 .. PUSH {r0,r1} 0x1005003e: 2000 . MOVS r0,#0 0x10050040: 0200 .. LSLS r0,r0,#8 0x10050042: 3000 .0 ADDS r0,#0 0x10050044: 0200 .. LSLS r0,r0,#8 0x10050046: 300c .0 ADDS r0,r0,#0xc 0x10050048: 0200 .. LSLS r0,r0,#8 0x1005004a: 3091 .0 ADDS r0,r0,#0x91 0x1005004c: 9001 .. STR r0,[sp,#4] 0x1005004e: bd01 .. POP {r0,pc}
Any ideas why this happens? Please let me know.
Thanks
No idea. But Keil should know. What does Keil-Support say?
Oh! I haven't asked keil support yet. I'll do that. Thank you for your help!