Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3582 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • Not Answered

    If I write the application on the M3, how hard it will be to compile it on M4 ? 0

    • Cortex-M3
    • Cortex-M4
    1765 views
    2 replies
    Latest over 4 years ago
    by MU234
  • Not Answered

    Memory Alignment for VSTM/VLDM Instructions on Cortex R52 0

    • Cortex-R52
    • Arm Assembly Language (ASM)
    1896 views
    1 reply
    Latest over 4 years ago
    by 42Bastian Schick
  • Answered

    MS-DOS for ARM Dual Core Cortex A5 Qualcomm Snapdragon S1 MSM7225a 0

    2794 views
    2 replies
    Latest over 4 years ago
    by Vicente Iñaki Cortes2008
  • Not Answered

    Exceptions.s and cache.s in Uboot 0

    2481 views
    3 replies
    Latest over 4 years ago
    by Chaitan
  • Not Answered

    Flash Patching in Cortex M7 0

    • Cortex-M7
    2084 views
    4 replies
    Latest over 4 years ago
    by SaiGautamJP
  • Answered

    STM32 UART DMA can receive first time correct then it receive nothing 0

    12372 views
    4 replies
    Latest over 4 years ago
    by neo_hoang
  • Not Answered

    Can cleaning a cache line overwrite recent changes by other bus masters? 0

    • Cache coherency
    2212 views
    3 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Answered

    AXI4 - Data before address - why? 0

    • Address
    • AXI4
    7855 views
    6 replies
    Latest over 4 years ago
    by af_23
  • Not Answered

    PMU 0

    3290 views
    4 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Suggested Answer

    How can I add external RAM for a Cortex M7 controller? 0

    • Cortex-M7
    5210 views
    3 replies
    Latest over 4 years ago
    by Bob Saget
  • Suggested Answer

    How to get the number of PMU architectural and microarchitectural events in A72 or R5F? 0

    2350 views
    1 reply
    Latest over 4 years ago
    by Willy Wolff Arm Employee Badge
  • Suggested Answer

    how to download CMSDK ip 0

    1835 views
    1 reply
    Latest over 4 years ago
    by Mahesh Arm Employee Badge
  • Answered

    Use of WVALID signal in AXI +1

    • AXI
    8315 views
    3 replies
    Latest over 4 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Disable Cache L1 et L2 Armv8 0

    • Cortex-A72
    • Cache
    • Armv8-A
    15096 views
    8 replies
    Latest over 4 years ago
    by Kael Hong
  • Not Answered

    lpc55s69 over the air update 0

    1594 views
    1 reply
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    axi problem 0

    9167 views
    6 replies
    Latest over 4 years ago
    by Burns
  • Not Answered

    Corstone SSE-300 FVP simulator 0

    • Cortex-M55
    • Arm Development Studio
    • Corstone SSE-300
    1373 views
    0 replies
    Started over 4 years ago
    by Sap1006
  • Not Answered

    IDE debug Error 0

    1880 views
    3 replies
    Latest over 4 years ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    Significance of the WVALID signal in AXI 0

    • AMBA
    • AXI
    6697 views
    3 replies
    Latest over 4 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    I.MX8.MINI(CORTEX A53) Unable to complete the conversion of exception level from EL2 to EL1 0

    3228 views
    3 replies
    Latest over 4 years ago
    by 42Bastian Schick
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
  • Armv8-M
  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
  • Cortex-A7
  • Cortex-A8
  • Cortex-A9
  • Cortex-M
  • Cortex-M0
  • Cortex-M3
  • Cortex-M4
  • Cortex-M7
  • Cortex-R
  • Interrupt
  • Linux
  • Memory
  • Memory Management Unit (MMU)
  • NEON
  • TrustZone