On a Cortex R, where ldm/stm are interruptible, can i use ldrex and strex for double words to pass from ISR to a task in this way?
STREXD, // Ignoring (yes, dumping it) if it actually failed to write , do no spin-lock or retry here at all
in Task :
LDREXD // load .. CLREX // clear exclusion
One core (2 in dual lock-step), no sharing mem with other cores. Will this work for automically write/read double words in the scenario one ISR feeding a task?
And yes, no buffering between them.
Having two (or more) ldrex in sequence with different addresses is IMHO an programming error. But this is by my understanding. I cannot cite any manual to "prove" this.