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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3579 Questions
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  • Answered

    AXI Atomic Access 0

    • AXI
    11626 views
    2 replies
    Latest over 10 years ago
    by Deepak
  • Answered

    EL1 behavior when MMU is off 0

    • EL1
    • EL3
    • EL2
    4905 views
    1 reply
    Latest over 10 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Difference between WFI and WFE +1

    36383 views
    2 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    Is there enough processing horsepower in the ARM1176 processor .... 0

    • Arm11
    4656 views
    2 replies
    Latest over 10 years ago
    by Paul Harbin
  • Answered

    Virtual Timers in ARM V8 +1

    • Hypervisor
    5965 views
    1 reply
    Latest over 10 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Virtual Interrupts and usage in ARM V8 +1

    • EL1
    • EL0
    • Generic Interrupt Controller
    4931 views
    1 reply
    Latest over 10 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Self Hosted Debug +1

    • Linux
    5037 views
    2 replies
    Latest over 10 years ago
    by techguyz
  • Answered

    Why in A64 the coprocessor is removed? 0

    • AArch64
    • NEON
    • AArch32
    7713 views
    3 replies
    Latest over 10 years ago
    by Mark Nicholson Arm Employee Badge
  • Answered

    Cortex M4 Unaligned access with STR single word access 0

    • Cortex-M
    • Cortex-M4
    9811 views
    7 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    A TCM problem 0

    • Arm11
    10766 views
    7 replies
    Latest over 10 years ago
    by Peter Harris Arm Employee Badge
  • Answered

    How to trap Guest data aborts +1

    • EL1
    • EL2
    • Generic Interrupt Controller
    • Linux
    10020 views
    8 replies
    Latest over 10 years ago
    by armdev
  • Answered

    How to get Cortex m3 soft core +1

    • Cortex-M0
    • Cortex-M3
    • Cortex-M
    4007 views
    3 replies
    Latest over 10 years ago
    by Sadanand Gulwadi
  • Not Answered

    Can an ACE master have multiple write channels ? 0

    • ACE
    • AXI4
    3091 views
    2 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    ARM SPEC score. +1

    • Cortex-A15
    • Cortex-A
    4930 views
    2 replies
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    Why does Cortex-R only support most two cores? 0

    • Cortex-R
    • Cortex-R5
    • Cortex-A
    • Cortex-R7
    4536 views
    2 replies
    Latest over 10 years ago
    by Jon Taylor Arm Employee Badge
  • Answered

    I want to know how to invalidate or clean to cache only used secure-world 0

    • big.LITTLE
    • Cache
    • Armv8-A
    11315 views
    6 replies
    Latest over 10 years ago
    by 박주병
  • Answered

    Thirdparty RTOS support for ARM V8 +1

    • Armv8-A
    • Armv8-R
    3379 views
    1 reply
    Latest over 10 years ago
    by Yasuhiko Koumoto
  • Answered

    Programming ARMv8 memory mapped registers +1

    • APB
    6863 views
    5 replies
    Latest over 10 years ago
    by Ravinder
  • Answered

    Non aligned access in arm v7 going into exception 0

    • Cache
    9230 views
    3 replies
    Latest over 10 years ago
    by David Wang Arm Employee Badge
  • Answered

    ARM Cortex-A7 generic timer 0

    • Cortex-A
    • Cortex-A7
    11369 views
    4 replies
    Latest over 10 years ago
    by hostia
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Topics being discussed in this forum
  • AArch64
  • AMBA
  • Arm Assembly Language (ASM)
  • Armv7-A
  • Armv8-A
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  • AXI
  • Cache
  • Cortex-A
  • Cortex-A53
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  • Linux
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  • Memory Management Unit (MMU)
  • NEON
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