Hi experts! I have a question about cache instruction.
DDI0406C_b_arm_architecture_reference_manual for Armv7 says
Effect of the Multiprocessing Extensions on All and set/way maintenance operations
The only architectural guarantee for the following instructions is that they apply to the caches or
branch predictors of the processor that performs the operation:
• Invalidate entire instruction cache, ICIALLU
• Invalidate all branch predictors, BPIALL
• Clean and Invalidate data or unified cache line by set/way, DCCISW
• Clean data or unified cache line by set/way, DCCSW
• Invalidate data or unified cache line by set/way, DCISW.
That is, these operations have an effect only on the processor that performs the operation.
In case of ICIALLU(Instruction Cache Invalidate All to PoU),
as I know, processors in same cluster share L2 cache and L2 is commonly PoU
so if ICIALLU have effect to PoU then I guess this will effect other processors.
I don't understand Why it says "operations have an effect only on the processor that performs the operation."
plus if snoop and CCI control cache properly then the other processors will have effect.
Thank you Martin. yours is very helpful.
I misunderstood the SCU. I thought one processor invalidates cache lines then snoop unit aware of it and invalidate the other caches.
Is there any way to broadcast to all the cores in the outer shareable domain?