Hello,
The following table is extracted from the Cortex-R4 whitepaper:
Could someone help me to explain that question:
My concern is that Cortex-R4 can take MOV as first instruction, ADD as second instruction to a dual-issue pair in C category means that it is not limited by the data-path pipelines resource.
So, Cortex-R4 should be able to extend the A category to a version with second instruction including a additional MOV instruction.
Why cannot use ADD(Some data processing instruction) as first instruction and MOV as second instruction?
Thanks
Hi,
I'm going to move this question to the ARM Processors community as the members there will be better placed to help you.
Regards,
Ash.
> Could someone help me to explain that question:
> My concern is that Cortex-R4 can take MOV as first instruction, ADD as second instruction to a dual-issue pair in C category means that it is not limited by the data-path pipelines resource.
> So, Cortex-R4 should be able to extend the A category to a version with second instruction including a additional MOV instruction.
> Why cannot use ADD(Some data processing instruction) as first instruction and MOV as second instruction?
The dual issue on the Cortex-R4 is restricted dual issue, this will have been a design decision to ensure that the processor has power efficiency for a specific PPA. The dual issue cannot work with any data dependency or internal feedback loops so the list you showed is the requirement for coding for the R4.
There is also the point that there is no need to extend the case 1 to include the MOV after the ADD (or other processing instruction) as the standard case above can be maintained by compiler technology to always schedule non-data dependent ADD/MOV pairs together so the need for PPA expensive hardware design is not needed.
I hope this helps
Sincerely thanks for your clear response!